Abstract: An integrated circuit includes logic circuits of NMOS and PMOS transistors, and memory cells with NMOS and PMOS transistors. A common NSD implant mask exposes source and drain regions of a logic NMOS transistor and a memory NMOS transistor. The source and drain regions of the logic NMOS transistor and the memory NMOS transistor are concurrently implanted at a cryogenic temperature with an amorphizing species followed by arsenic. Phosphorus is concurrently implanted in the source and drain regions of the logic NMOS transistor and the memory NMOS transistor. The source and drain regions of the logic NMOS transistor are further implanted with phosphorus at a non-cryogenic temperature while the memory NMOS transistor is covered by a mask which blocks the phosphorus.

Abstract: An integrated circuit containing a stacked bipolar transistor which includes two bipolar transistors connected in series is disclosed. Each bipolar transistor includes a breakdown inducing feature. The breakdown inducing features have reflection symmetry with respect to each other. A process for forming an integrated circuit containing a stacked bipolar transistor which includes two bipolar transistors connected in series, with breakdown inducing features having reflection symmetry, is also disclosed.

Abstract: An example embodiment provides a resizer in an image processing system. The resizer includes a receiving module that receives pixel data representative of an image. A triple line buffer is coupled to the receiving module that stores the pixel data in response to a write control signal from control logic. The triple line buffer is operated as a circular buffer. The resizer further includes a resizer core that reads pixel data from the triple line buffer in response to a read control signal from the control logic. The pixel data is replicated to up-scale the image vertically according to a vertical up-scale ratio such that the resizer achieves a maximum input data rate and also eliminates an overflow condition in the resizer. The vertical up-scale ratio is a fraction.

Abstract: A gate driving circuit includes a driving stage configured to receive an input signal and generate a gate drive signal for a gate of a transistor switch. The gate driving circuit also includes an LC circuit having an inductor and a gate capacitance of the transistor switch. The LC circuit is configured so that a pulse in the gate drive signal generates a ringing in the LC circuit at a resonance frequency of the LC circuit to transfer energy into and out of the gate capacitance of the transistor switch. A switch could selectively couple the gate of the transistor switch to ground in order to discharge the gate capacitance. A control circuit could be used to provide the input signal, and the control circuit could be configured to regulate a duty cycle of the gate drive signal by adjusting an off-time between consecutive pulses in the input signal.

Abstract: An electronic device includes an integrated circuit with a FRAM memory and an integrated capacitor connected between a power supply for the FRAM memory and ground. The integrated capacitor has a capacitance sufficient to store the charge necessary for a complete read-and-write-back cycle of the FRAM memory. When granting read-access to the FRAM memory, the FRAM memory is supplied by the integrated capacitor which is then disconnected from the integrated circuit power supply. Upon receiving a request for a read-access to the FRAM memory, a charge detector detects whether the internal capacitor is sufficiently charged for a complete read-and-write-back cycle of the FRAM memory. Read-access to the FRAM memory is only granted if the internal capacitor is sufficiently charged and disconnected from the power supply. An alternative embodiment alternately charges and powers the FRAM from two integrated capacitors.

Abstract: An integrated circuit (70) having parallel scan paths (824-842, 924-942) includes a pair or pairs of scan distributor (800,900) and scan collector (844,944) circuits. The scan paths apply stimulus test data to functional circuits (702) on the integrated circuit and receive response test data from the functional circuits. A scan distributor circuit (800) receives serial test data from a peripheral bond pad (802) and distributes it to each parallel scan path. A scan collector circuit (844) collects test data from the parallel scan paths and applies it to a peripheral bond pad (866). This enables more parallel scan paths of shorter length to connect to the functional circuits. The scan distributor and collector circuits can be respectively connected in series to provide parallel connections to more parallel scan paths. Additionally multiplexer circuits (886,890) can selectively connect pairs of scan distributor and collector circuits together.

Abstract: In an embodiment of the invention, a non-volatile anti-fuse memory cell is disclosed. The memory cell consists of a programmable n-channel diode-connectable transistor. The poly-silicon gate of the transistor has two portions. One portion is doped more highly than a second portion. The transistor also has a source with two portions where one portion of the source is doped more highly than a second portion. The portion of the gate that is physically closer to the source is more lightly doped than the other portion of the poly-silicon gate. The portion of the source that is physically closer to the lightly doped portion of the poly-silicone gate is lightly doped with respect to the other portion of the source. When the transistor is programmed, a rupture in the insulator will most likely occur in the portion of the poly-silicone gate that is heavily doped.

Abstract: A controller for a DC/DC converter can include a first error analog to digital converter (EADC) configured to detect a primary voltage from a secondary side of a transformer and generate a first error signal corresponding to the primary voltage. The first error signal is generated based on a comparison between a first reference voltage and the detected primary voltage. A first accelerator can be configured to process the first error signal and generate a first compensation signal that is a primary voltage variation signal used for feedforward control. A second EADC and a second accelerator can be configured to provide a output voltage feedback control. A compensation signal of the first accelerator can be used to scale the second accelerator output to facilitate fast feedforward control.

Abstract: A method of local tone mapping of a high dynamic range (HDR) image is provided that includes dividing a luminance image of the HDR image into overlapping blocks and computing a local tone curve for each block, computing a tone mapped value for each pixel of the luminance image as a weighted sum of values computed by applying local tone curves of neighboring blocks to the pixel value, computing a gain for each pixel as a ratio of the tone mapped value to the value of the pixel, and applying the gains to corresponding pixels in the HDR image. A weight for each value is computed based on distance from the pixel to the center point of the block having the local tone curve applied to compute the value and the intensity difference between the value of the pixel and the block mean pixel value.

Abstract: A radiation sensor includes an integrated circuit radiation sensor chip (1A) including first (7) and second (8) thermopile junctions connected in series to form a thermopile (7,8) within a dielectric stack (3). The first thermopile junction (7) is insulated from a substrate (2) of the chip. A resistive heater (6) in the dielectric stack for heating the first thermopile junction is coupled to a calibration circuit (67) for calibrating responsivity of the thermopile (7,8). The calibration circuit causes a current flow in the heater and multiplies the current by a resulting voltage across the heater to determine power dissipation. A resulting thermoelectric voltage (Vout) of the thermopile (7,8) is divided by the power to provide the responsivity of the sensor.

Abstract: A method of generating a high dynamic range (HDR) image is provided that includes capturing a long exposure image and a short exposure image of a scene, computing a merging weight for each pixel location of the long exposure image based on a pixel value of the pixel location and a saturation threshold, and computing a pixel value for each pixel location of the HDR image as a weighted sum of corresponding pixel values in the long exposure image and the short exposure image, wherein a weight applied to a pixel value of the pixel location of the short exposure image and a weight applied to a pixel value of the pixel location in the pixel long exposure image are determined based on the merging weight computed for the pixel location and responsive to motion in a scene of the long exposure image and the short exposure image.

Abstract: A system and method for managing power in a subnet having a hub in communication with one or more nodes is disclosed. The hub and nodes communicate using one or more non-contention access methods, such as scheduled, polled or posted access. The node may enter a sleep or hibernation state while no scheduled, polled or posted allocation interval is pending. The hibernation state allows the node to hibernate through one or more entire beacon periods. In the sleep state, the node may be asleep between any scheduled, polled and posted allocation intervals for the node or during another node's scheduled allocation interval in a current beacon period. By selecting which access scheme is in use, the node and hub can increase the node's chances to be in hibernation or sleep state and minimize power consumption.

Abstract: A method of displaying an image includes alternating an active state of each of a plurality of light sources. The light sources each generate a light beam when active. The alternating includes deactivating an active light source before an output of a light beam from the active light sources falls below a first predetermined threshold. The alternating further includes activating a deactivated light source only after an output of the inactive light source reaches a second predetermined threshold. The method further includes receiving each of the light beams at a spatial light modulator.

Abstract: A method of forming semiconductor die includes forming a layer of polymer or a precursor of the polymer on a bottomside of a substrate having a topside including active circuitry and a bottomside, and a plurality of through-substrate-vias (TSVs). The TSVs have a liner including at least a dielectric liner and an inner metal core that extends to TSV tips that protrude from the bottomside. The layer of polymer or precursor and liner cover the plurality of TSV tips, and the layer of polymer or precursor is between the TSV tips on the bottomside. The polymer or precursor and the liner are removed from over a top of the TSV tips to reveal the inner metal core.

Abstract: This invention optimizes non-shared accesses and avoids dependencies across coherent endpoints to ensure bandwidth across the system even when sharing. The coherence controller is distributed across all coherent endpoints. The coherence controller for each memory endpoint keeps a state around for each coherent access to ensure the proper ordering of events. The coherence controller of this invention uses First-In-First-Out allocation to ensure full utilization of the resources before stalling and simplicity of implementation. The coherence controller provides Snoop Command/Response ID Allocation per memory endpoint.

Abstract: A semiconductor device contains a photodiode which has a plurality of p-n junctions disposed in a stack. Two contact structures on the semiconductor device are connected across at least one of the junctions to allow electrical connection to an external detection circuit, so that signal current from incident light on the photodiode which generates electron-hole pairs across the connected junction may be sensed by the external detection circuit. At least one of the junctions is electrically shorted at the semiconductor device, so that signal current from the shorted junction may not be sensed by the external detection circuit.

Abstract: A code word is received that was derived from a plurality of smaller code words that represent a data word of 2m data bits and a plurality of error correction code bits. The code word is converted into the plurality of smaller code words and syndromes are computed by multiplying each of the plurality of smaller code words by a check matrix. The syndrome words are processed to determine a number of errors that exist in each of the plurality of smaller code words. A portion of the syndrome words is processed to determine locations of possible errors within the plurality of smaller code words. Up to two errors may be corrected and up to three errors may be detected in the code word by using the number of errors and the locations of possible errors to determine erroneous bits in the code word.

Abstract: Systems and methods for adaptive modulation and coding with frame size adjustment are described. In various implementations, these systems and methods may be applicable to Power Line Communications (PLC). For example, a method may include identifying a temporal region of a cyclostationary noise over which a frame is to be sent across a PLC network, the cyclostationary noise having a plurality of temporal regions, each of the plurality of temporal regions having a distinct spectral shape. The method may also include applying a given one of a plurality of Modulation and Coding Schemes (MCSs) to the frame to produce a modulated frame, wherein the given one of the plurality of MCSs is selected based, least in part, upon the spectral shape corresponding to the identified temporal region. The method may further include transmitting the modulated frame across the PLC network, at least in part, over the identified temporal region.

Abstract: Timely testing of die on wafer reduces the cost to manufacture ICs. This disclosure describes a die test structure and process to reduce test time by adding test pads on the top surface of the die. The added test pads allow a tester to probe and test more circuits within the die simultaneously. Also, the added test pads contribute to a reduction in the amount of test wiring overhead traditionally required to access and test circuits within a die, thus reducing die size.

Abstract: Various embodiments of an amplifier circuit are provided. In one embodiment, the amplifier circuit includes an input differential circuitry configured to convert a pair of input differential voltage signals to a pair of differential current signals. The amplifier circuit includes a cascode circuitry operable to mirror the pair of differential current signals received from the first output terminal and the second output terminal to an output terminal of the first cascode transistor and an output terminal of the second cascode transistor. The amplifier circuit includes a current control circuit operable to divert an amount of bias current to reduce a current through the cascode circuitry, to thereby reduce a load of the amplifier circuit, the reduction in the load of the amplifier circuit allowing a reduction in current through the input differential circuitry for maintaining a predetermined bandwidth of the amplifier circuit.