Abstract: This invention is an integrated memory controller/interconnect that provides very high bandwidth access to both on-chip memory and externally connected off-chip memory. This invention includes an arbitration for all memory endpoints including priority, fairness, and starvation bounds; virtualization; and error detection and correction hardware to protect the on-chip SRAM banks including automated scrubbing.

Abstract: Embodiments of the invention provide a method for discriminating between two types of encoding schemes for the frame control header (FCH) used in G3-type narrow band OFDM communications. The two modes for encoding are Differential with respect to the previous Symbol (DS) and Differential with respect to the Preamble (DP).

Abstract: A system and method for minimizing or preventing interference between wireless networks is disclosed. A network hub broadcasts a beacon signal within repeating beacon periods. The position of the beacon signal shifts within each beacon period based upon a predetermined pseudo-random sequence. The beacon signal includes data identifying the current beacon shift sequence and the current phase of the sequence. Neighboring hubs independently or jointly determine and broadcast their own beacon shift sequences and phases for their respective networks from a predetermined list. Nodes connected with the network hubs are assigned allocation intervals having a start time that is set relative to the beacon signal. The start time and duration of the allocation interval wraps around the beacon period if the allocation-interval would otherwise start or continue in a next beacon period.

Abstract: A method for operating a user interface on a system in which objects are displayed on a touch sensitive display screen. A touch coordinate is received from the touch sensitive display screen indicative of a touch location on the display screen. A search area surrounding the touch coordinate is searched for an object. The search area has an initial minimum size. If an object is found within the initial minimum search area it is identified. If no object is found, then the size of the search area is incrementally increased and searched until a final maximum size is reached. If no object is found, then the search is terminated.

Abstract: An apparatus is provided. There is an input terminal that is configured to receive an input signal from a optical receiver and an output terminal. First and second integrators are coupled between the input and output terminals. In the second integrator, there is a current source that is coupled to the input terminal, a first resistor that is coupled to the output terminal, and a second resistor. Also, there is an amplifier having a first input, a second input, and an output, where the first resistor is coupled to the first input of the amplifier and where the second input of the amplifier is configured to receive a reference voltage. A transistor is coupled between the current source the second resistor and is coupled to the output of the amplifier at its gate. A capacitor is also coupled between the first input of the amplifier and the second resistor.

Abstract: An apparatus is provided. In the apparatus, there is an antenna package and an integrated circuit (IC). A circuit trace assembly is secured to the IC. A coupler (with an antenna assembly and a high impedance surface (HIS)) is secured to the circuit trace assembly. An antenna assembly has a window region, a conductive region that substantially surrounds the window region, a circular patch antenna that is in communication with the IC, and an elliptical patch antenna that is located within the window region, that is extends over at least a portion of the circular patch antenna, and that is in communication with the circular patch antenna. The HIS substantially surrounds the antenna assembly.

Abstract: A method of detecting a signal in radio frequency identification (RFID) transponder (FIG. 1) is disclosed. The method includes receiving a signal (FIG. 7) having a first time in a first logic state (high) and having a second time in a second logic state (low). A weight (700, 702) is determined in response to the first time and the second time. An output signal (from A2D) is produced in response to the weight and one of the first and second logic states.

Abstract: An electronic device, a fiber-optic communication system comprising the electronic device and a method of operating the electronic device are provided. The electronic device comprises a transimpedance-type amplifier having a transimpedance stage comprising an amplifier which is coupled in series with an input node. A feedback resistor is coupled in series between an output node of the amplifier and an inverting input node of the amplifier to provide a virtual ground node which is coupled to the input node, the inverting input node of the amplifier and to the feedback resistor. A current source is coupled to the virtual ground node so as to compensate for an offset current in an input signal which is coupled to the input node of the electronic device. Further, the electronic device comprises a control stage which is configured to control the current source as a function of a current through the feedback transistor.

Abstract: The MSMC (Multicore Shared Memory Controller) described is a module designed to manage traffic between multiple processor cores, other mastering peripherals or DMA, and the EMIF (External Memory InterFace)in a multicore SoC. Each processor has an associated return buffer allowing out of order responses of memory read data and cache snoop responses to ensure maximum bandwidth at the endpoints, and all endpoints receive status messages to simplify the return queue.

Abstract: A coherence maintenance address queue tracks each memory access from receipt until the memory reports the access complete. The address of each new access is compared against the address of all entries in the queue. This check is made when the access is ready to transmit to the memory. If there is no address match, then the current access does not conflict with any pending access. If there is an address match, the current access is stalled. The multi-core shared memory controller would then typically proceed to another access waiting a slot to the endpoint memory. Stored addresses in the coherence maintenance address queue are retired when the endpoint memory reports completion of the operation. At this point the access is no longer a hazard to following operations.

Abstract: This invention speeds operation for coherence writes to shared memory. This invention immediately commits to the memory endpoint coherence write data. Thus this data will be available earlier than if the memory controller stalled this write pending snoop responses. This invention computes write enable strobes for the coherence write data based upon the cache dirty tags. This invention initiates a snoop cycle based upon the address of the coherence write. The stored write enable strobes enable determination of which data to write to the endpoint memory upon a cached and dirty snoop response.

Abstract: An asynchronous dual domain bridge is implemented between the cache coherent master and the coherent system interconnect. The bridge has 2 halves, one in each clock/powerdown domain-master and interconnect. The powerdown mechanism is isolated to just the asynchronous bridge implemented between the master and the interconnect with a basic request/acknowledge handshake between the master subsystem and the asynchronous bridge.

Abstract: A method of compressing digital image data is provided that includes selecting an entropy code for encoding a line of pixels in the digital image data, wherein the entropy code is selected from a plurality of variable length entropy codes, using spatial prediction to compute a pixel predictor and a pixel residual for a pixel in the line of pixels, and selectively encoding the pixel residual using one of the entropy code or run mode encoding.

Abstract: A method of generating an integrated circuit with a DPT compatible interconnect pattern using a reduced DPT compatible design rule set and color covers. A method of operating a computer to generate an integrated circuit with a DPT compatible interconnect pattern using a reduced DPT compatible design rule set and using color covers. A reduced DPT compatible design rule set.

Abstract: A method of fabricating gate level electrodes and interconnects in an integrated circuit, and an integrated circuit so fabricated, with improved process margin for the gate level interconnects of a width near the critical dimension. Off-axis illumination, as used in the photolithography of deep sub-micron critical dimension, is facilitated by the patterned features having a preferred orientation in a common direction, with a pitch constrained to within a relatively narrow range. Interconnects in that same gate level, for example “field poly” interconnects, that run parallel to an array of gate elements are placed within a specified distance range from the ends of the gate elements, or at a distance sufficient to allow sub-resolution assist features.

Abstract: A prefetch unit generates prefetch addresses in response to an initial received memory read request, an address associated with the initial received memory read request, a line length of the requestor of the initial received memory read request, and a request type width of the initial received memory read request. Prefetch operations are generated using the generated prefetch addresses, wherein each generated prefetch address is stored in a prefetch buffer slot that is selected by a prefetch FIFO (First In First Out) prefetch counter. Subsequent hits on the prefetcher result in returning prefetched data to the requestor in response to a subsequent memory read request received after the initial received memory read request.

Abstract: The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer (110) beneath the gate dielectric (50) and source and drain regions (80) of a MOS transistor. The carbon containing layer (110) will prevent the diffusion of dopants into the region (40) directly beneath the gate dielectric layer (50).

Abstract: This invention is a memory system with parity generation which selectively forms and stores parity bits of corresponding plural data sources. The parity generation and storage depends upon the state of a global suspend bit and a global enable bit, and parity detection/correction corresponding to each data source.

Abstract: The present invention relates to data manipulation and in particular incrementing, decrementing and comparing binary coded numbers, notably the manipulation of thermometer codes and the performance of arithmetic operations thereon. A method of processing data is provides which comprises receiving a series of data samples, each sample being represented as an N-bit thermometer code, wherein the most significant bit thereof represents the sign of the data sample value Y(n) and the remaining N?1 bits represent the magnitude of the data sample and executing a predetermined sequence of arithmetic operations directly on the series of N-bit thermometer code data samples to determine one of two values for each data sample, without any recoding of the thermometer code data samples.

Abstract: Architecture for VBUS pulsing in an Ultra Deep Sub Micron (UDSM) process for ensuring USB-OTG (On The Go) session request protocol, the architecture being of the type wherein at least a charging circuit is deployed, uses a diode-means connected in a forward path of the charging circuit. The architecture might include a diode-divider including nodes and connected from VBUS in said charging circuit. One embodiment uses both charging and discharging circuits comprising transistors. The charging circuit transistor might comprise a PMOS transistor and the discharging circuit transistor might comprise a NMOS transistor. The architecture might include a three resistance string of a total resistance value approximating 100K Ohms connected between said VBUS and ground, wherein the discharging circuit transistor might comprise a drain extended NMOS transistor. The charging and discharging circuit transistors have VDS and VGD of about 3.6V, whereby high VGS transistors are not needed.