Abstract: A method of encoding samples in a digital signal is provided that includes receiving a frame of N samples of the digital signal, determining L possible distinct data values in the N samples, determining a reference data value in the L possible distinct data values and a coding order of L?1 remaining possible distinct data values, wherein each of the L?1 remaining possible distinct data values is mapped to a position in the coding order, decomposing the N samples into L?1 coding vectors based on the coding order, wherein each coding vector identifies the locations of one of the L?1 remaining possible distinct data values in the N samples, and encoding the L?1 coding vectors.

Abstract: A system and method for scrambling and time-hopping in an ultra-wideband wireless network. In one embodiment, a wireless device includes a symbol mapper and a dynamic chip scrambler. The dynamic chip scrambler is configured to scramble each of a plurality of consecutive bursts of a time-hopped packet according to a pseudo-random scrambling sequence that varies from burst to burst.

Abstract: In at least some embodiments, a receiver for a wireless communication system is provided. The receiver includes an equalizer that provides an equalized channel matrix. The receiver also includes scaling logic coupled to the equalizer, the scaling logic selectively scales coefficients of the equalized channel matrix. The receiver also includes a decoder coupled to the scaling logic. The decoder decodes a signal based on the equalized channel matrix with scaled coefficients.

Abstract: A test controller applies test stimulus signals to the input pads of plural die on a wafer in parallel. The test controller also applies encoded test response signals to the output pads of the plural die in parallel. The encoded test response signals are decoded on the die and compared to core test response signals produced from applying the test stimulus signals to core circuits on the die. The comparison produces pass/fail signals that are loaded in to scan cells of an IEEE 1149.1 scan path. The pass/fail signals then may be scanned out of the die to determine the results of the test.

Abstract: An optical disk drive system associated with a laser diode is described. The optical disk drive system comprises a current generator for receiving input signals; a current switch coupled to receive timing signals; a current driver coupled to receive output signals from the current switch and the current generator, the current driver further comprising a driver with wave shape control selected from the group consisting of a laser diode read driver and a laser diode write driver, wherein the driver with shape control is operative for transmitting at least one output signal that is a scaled version of at least one of the output signals received from the current generator, wherein the current driver is operative for transmitting at least one output signal driving the laser diode.

Abstract: An integrated circuit package may be formed using a leadframe having an open space extending therethrough. A shunt is located within the open space such that it is not in contact with any portion of the leadframe. Tape may be applied to the lower surface of the leadframe to support the shunt and hold it in place relative to the leadframe until wirebonding and encapsulation have been completed. Thereafter, the tape may be removed.

Abstract: Multiplier circuitry includes first multiplier circuit including a first transistor having an emitter coupled to a first conductor, a base coupled to a second conductor, and a collector coupled to a third conductor, a second transistor having an emitter coupled to the first conductor, a base coupled to a fourth conductor, and a collector coupled to a fifth conductor, a third transistor having an emitter coupled to the second conductor and a base and collector coupled to a supply voltage, and a fourth transistor having an emitter coupled to the fourth conductor and a base and collector coupled to the supply voltage. Chopper includes a first switch to provide a chopped differential signal between the second and fourth conductors and a second switch for un-chopping a first differential output signal produced between the third and fifth conductors to provide an un-chopped differential output signal between the third and fifth conductors.

Abstract: A sampled CMOS switch includes first and second NMOS devices in series between input and output nodes. The first and second NMOS devices are activated by a sample signal. A pair of low-voltage DEPMOS devices is connected in a “T” configuration between the input and output nodes. The low-voltage DEPMOS devices are activated by an inverted sample signal. A feedback circuit includes the DEPMOS devices together with a third high-voltage NMOS device and a current source. The third NMOS device is controlled by a signal on the input node. A switch switchably connects an analog voltage source to a source of the third NMOS device and gates of the DEPMOS devices in accordance with a phase of an inverted sample signal. The construction of the sampled CMOS switch enables the protection of the gate oxide insulation of the low-voltage DEPMOS transistors from high voltage damage.

Abstract: A clock divider circuit. The clock divider receives m input clock signals each of the same frequency. Each input clock signal after the first has a phase offset of 2?/m from the previous input clock signal. The clock divider divides the frequency of the input clock signals by an integer of division K. The clock divider includes a counter that receives the first input clock signal and provides one or more count signals. The clock divider also includes m flip-flops, of which a first flip-flop receives the first input clock signal at its clock input and provides a first clock output signal. Each flip-flop after the first receives an input clock signal at its clock input and provides a clock output signal, each clock output signal after the first having a 2?K/m phase offset from the previous clock output signal.

Abstract: A clock generation circuit in an IC is provided for mitigating signal interferences caused by an aggressor block operable on a first clock signal with a frequency range of a victim block. The clock generation circuit includes a gating circuit configured to perform gating of a second clock signal to generate a third clock signal based on control signal. An average frequency of the third clock signal is substantially matched to a frequency of the first clock signal, and harmonics of the third clock signal do not interfere with the frequency range of the victim block. The clock generation circuit further includes a FIFO buffer circuit configured to receive the first clock signal as a write clock and the third clock signal as read clock, and a control circuit for generating the control signal based on an occupancy level of FIFO buffer circuit and a plurality of random numbers.

Abstract: A buck switching voltage regulator, with high side and low side switching transistors, includes mode control circuitry for switching between PWM and PFM modes based on sensing inductor current through the low side switch during switching cycle OFF times (inductor discharge). Mode switching is based on comparing a an integrated inductor current sense signal with an integrated reference signal corresponding to a predefined average inductor current IAVE. In one embodiment, a mode switching condition is based in part on [IVALLEY=21AVE?IPEAK], where IPEAK is a detected peak inductor current at the beginning of an OFF time, and IVALLEY is an inductor current value determined by IAVE and IPEAK.

Abstract: The disclosure describes a novel method and apparatus for allowing a controller to access a bus router using a communication occurring in response to one edge of a clock to select one or more devices for access using a communication occurring on the opposite edge of the clock. Additional embodiments are also provided and described in the disclosure.

Abstract: In the L2 FIFO architecture incoming frames are stored in a multi bank FIFO to enable offloading the programmable real-time unit to do other tasks. The L2 FIFO buffers data coming from the L1 FIFO, reducing the polling time for received data. Status is always checked for errors before processing the data and updating the state variables. Implementing a state machine to perform some of the checks results in a PRU utilization that is not a function of the bytes that need to be processed.

Abstract: Pulse width modulation controller apparatus and techniques are presented for balancing output currents of DC-DC converter stages in a multi-stage DC-DC conversion system in which a reference current is provided according to an input voltage and the value of a connected resistor, and a correction current output signal is generated that represents the difference between an average converter stage load current and the local load current, with the on-time of the PWM output signal being generated by charging a capacitance using a charging current obtained by offsetting the reference current output signal with the correction current output signal.

Abstract: For controlling operation of a vehicle, at least one camera captures an image of a screen on which a user places an object having features distinguishing the user. A controller detects the features in the image and analyzes the features to distinguish the user. In response to distinguishing the user, the controller outputs signals for controlling operation of the vehicle. A projector receives information from the controller and projects the information onto the screen, so that the information is displayed on the screen for viewing by the user.

Abstract: Scratch pad register banks are used as shared fast access storage between processors in a multi processor system. Instead of the usual one to one register mapping between the processors and the scratch pad register banks, an any to any mapping is implemented. The utilization of the scratch pad register banks is improved as the any to any mapping of the registers allow the storage of any processor register anywhere in the scratch pad register bank.

Abstract: Topology discovery of a target system having a plurality of components coupled with a scan topology may be performed by driving a low logic value on the data input signal and a data output signal of the scan topology. An input data value and an output data value for each of the plurality of components is sampled and recorded. A low logic value is then scanned through the scan path and recorded at each component. The scan topology may be determined based on the recorded data values and the recorded scan values.

Abstract: A control circuit configured to control a switching power supply including a ramp generator configured to generate a triangular waveform. A comparator is configured to generate a series of pulse width modulated (PWM) pulses at a first frequency and to regulate the switching power supply. The ramp generator includes a capacitor, a charging current source configured to provide a charging current to charge the capacitor, and a discharging current source configured to provide a discharging current to discharge the capacitor. The ramp generator also includes a closed loop current balancing current source configured to balance the currents from the charging and discharging current sources to establish a substantially zero direct current (DC) bias across the capacitor. The controller also includes a multi-phase configuration to provide a stackable multi-channel architecture.

Abstract: A method of camera pose estimation is provided that includes capturing a model image of a scene at a canonical camera pose, generating an image library from warped images of the model image and the model image, wherein each warped image is a transformation of the model image at a different pre-determined camera pose, capturing an image of the scene as a user moves the camera, reporting the current camera pose as a camera pose of the image when the image is acceptable, conditionally adding the first image to the image library when the first image is acceptable, and re-initializing the current camera pose to a camera pose selected from the image library when the first image is not acceptable.

Abstract: A digital circuit includes at least one input node, a biasing circuit, and a digital baseband circuit. The input node receives a digital signal including samples at a plurality of sample instances, the samples including a positive sample and a negative sample and represented by first plurality of bits. The biasing circuit generates a biased digital signal by adding a bias value to the digital signal so as to change the positive sample and the negative sample to first sample and second sample respectively and represented by second plurality of bits. The digital baseband circuit is configured to receive and process the biased digital signal such that reduced current consumption is realized based on a number of bit toggles in the second plurality of bits being less than a number of bit toggles in the first plurality of bits.