Abstract: In accordance with at least some embodiments, a system includes a processing entity configured to run multiple threads. The system also includes a direct memory access (DMA) engine coupled to the processing entity, the DMA engine being configured to track DMA in-flight status information for each of a plurality of DMA channels. The processing entity is configured to manage overlapping DMA requests to a DMA channel of the DMA engine based on said DMA in-flight status information.

Abstract: An integrated circuit is formed by identifying process parameters of a plurality of process steps for the first partial lot containing the integrated circuit; confirming the number of wafers in the first partial lot is less than the wafer carrier capacity; examining lots upstream of the partial lot and identifying a second partial lot which can be combined with the first partial lot into a single wafer carrier and which can be processed with the first partial lot; combining the wafers of the partial lots into a single wafer carrier; processing the partial lots through the plurality of process steps; and performing a multi-lot verification process. The multi-lot verification process determines if all wafers in the partial lots have completed the process step; determines if any wafers in the partial lots are on hold; and determining if all wafers in the partial lots are in a same material carrier.

Abstract: With batteries or cells, particularly lithium ion cells, it is important to determine when one or more cells have entered a fault condition (i.e., overvoltage or undervoltage). Conventional circuits employ measuring circuits that use multiple bandgap circuits and high voltage components. These conventional circuits, however, consume a great deal of area because of the use of these multiple bandgap circuits and the high voltage components. Here, a circuit is provided that reduces the number of bandgap circuits and reduces the number of high voltage components, reducing the area consumed and reducing the overall cost of production compared to conventional circuits.

Abstract: A system and method are provided that are operable for network communications that promote network devices to receive a transmit request, transmit a first part of a frame by a physical layer without a second part of the frame from a medium access control layer, and request the second part of the frame by the physical layer from the medium access control layer. These systems and methods also allow, in some embodiments, for the transmitting of the second part of the frame by the physical layer with data from the medium access control layer.

Abstract: An SRAM device and method of forming MOS transistors of the device having reduced defects associated with selective epitaxial growth in moat tip regions is discussed. The SRAM device comprises a core region and a logic region, logic transistors within the logic region of the SRAM, and selective epitaxial regions grown on both source and drain regions; and memory cell transistors within the core region of the SRAM, and having the selective epitaxial regions grown on only one of the source and drain regions. One method of forming the MOS transistors of the SRAM cell comprises forming a gate structure over a first conductivity type substrate to define a channel therein, masking one of the source and drain regions in the core region, forming a recess in the substrate of the unmasked side of the channel, epitaxially growing SiGe in the recess, removing the mask, and forming the source and drain extension regions in source/drain regions.

Abstract: A bus monitoring and debugging system operating independently without impacting the normal operation of the CPU and without adding any overhead to the application being monitored. Users are alerted to timing problems as they occur, and bus statistics that are relevant to providing insight to system operation are automatically captured. Logging of relevant events may be enabled or disabled when a sliding time window expires, or alternatively by external trigger events.

Abstract: Operating a state machine includes enabling operation of the state machine upon receiving a signal indicating a change from operation of a test access port to a scan test port. The process maintains the state machine in an IDLE 1 state while receiving a scan test port capture signal and transitions the state machine to an IDLE 2 state when receiving a scan test port shift signal. The process then transitions the state machine to a SEQUENCE 1 state, then to a SEQUENCE 2 state, and then to a SEQUENCE 3 state when receiving sequential scan test port capture signals. The state machine then transitions to an UNLOCK TAP state and then back to the IDLE 1 state when receiving sequential scan test port shift signals on the test mode select/capture select lead.

Abstract: A display system and method of producing images with high dynamic range are provided. The display system employs multiple light valves for projecting a portion of the image onto another.

Abstract: Multiprocessor systems often share access to a centralized memory and experience conflicting access requests. An arbitration unit mediates priorities of requestor preferably ensuring both priority and fairness. In this invention upon an access conflict the arbitrator grants access to one requestor having the highest priority level and stalls other conflicting requestors. If plural requestors have the same priority level, the arbiter grants access to one and stalls the others. The arbiter then adjusts the priority levels of the requestors. The priority of the requestor granted access is decreased by the number of stalled requestors. The stalled requestors have their priority levels increased by one. The arbitration decision is thus based on the stall history and the caused stall history of each requestor.

Abstract: A method, system and apparatus of lossy compression technique for video encoder bandwidth reduction using compression error data are disclosed. In one embodiment, a method includes storing an error data from a compression of an original reference data in an off-chip memory, accessing the error data during a motion compensation operation, and performing the motion compensation operation by applying the error data through an algorithm (e.g., determined by the method of storing the error data). The method may include generating a predicted frame in the motion compensation operation using a motion vector and an on-chip video data. In addition, the method may include determining the error data as a difference between a compressed reference data (e.g., is created by compressing the original reference data) and an original reference data (e.g., reconstructed from a prior predicted frame and a decompressed encoder data).

Abstract: A bidirectional electrostatic discharge (ESD) protection device includes a substrate having a topside semiconductor surface that includes a first silicon controlled rectifier (SCR) and a second SCR formed therein including a patterned p-buried layer (PBL) including a plurality of PBL regions. The first SCR includes a first and second n-channel remote drain MOS device each having a gate, a source within a p-body, and sharing a first merged drain. The second SCR includes a third and a fourth n-channel remote drain MOS device each having a gate, a source within a p-body, and sharing a second merged drain. The plurality of PBL regions are directly under at least a portion of the sources while being excluded from being directly under either of the merged drains.

Abstract: A system and method for sharing a communications link between multiple protocols is described. A system includes a communications interface configured to exchange information with other systems using at least one of a plurality of protocols; a protocol select register that stores a value that selects a protocol from among the plurality of protocols to become an active protocol; and a state machine accessible to the communications interface, the state machine used to control the exchange of information through the communications interface according to the active protocol. The active protocol is used by the communications interface to exchange information while the remaining protocols of the plurality of protocols remain inactive. The state machine sequences through a series of states that cause the communications interface to operate according to the active protocol, and that are designated as inert sequences under the remaining protocols.

Abstract: A semiconductor die includes a first contact stack including a first UBM pad on a first die pad, a second contact stack including a second UBM pad on a second die pad, and a third contact stack including a third UBM pad on a third die pad. The second UBM pad perimeter is shorter than the first UBM pad perimeter, and the third UBM pad perimeter is longer than the second UBM pad perimeter. A first solder bump is on the first UBM pad, a second solder bump is on the second UBM pad, and a third solder bump is on the third UBM pad. The first solder bump, second solder bump and third solder bump all have different sizes.

Abstract: In accordance with at least some embodiments, a digital signal processor (DSP) includes an instruction fetch unit and an instruction decode unit in communication with the instruction fetch unit. The DSP also includes a register set and a plurality of work units in communication with the instruction decode unit. The register set includes a plurality of legacy predicate registers. Separate from the legacy predicate registers, a plurality of on-demand predicate registers are selectively signaled without changing the opcode space for the DSP.

Abstract: An apparatus is provided. An integrated circuit or IC is secured to a package housing. The IC has an IC substrate and an epitaxial layer formed over the substrate and having an active region and an upper surface. The upper surface is substantially exposed, and bond pads are formed over the epitaxial layer. Bond fixtures are each secured to and in electrical contact with at least one of the bond pads and with the package housing. A fill formed over at least a portion of the epitaxial layer so as to substantially encapsulate the active region, where the fill has a dielectric constant that is substantially equivalent to the dielectric constant of air. Additionally, the fill has a thickness, where the thickness is sufficiently large enough to confine parasitics of the active region at the upper surface of the epitaxial layer.

Abstract: A packet filter (2500) for incoming communications packets includes extractor circuitry (2510) operable to extract data from a packet, and packet processor circuitry (2520) operable to concurrently mask (3010) the packet data from the extractor circuitry (2510), perform an arithmetic/logic operation (3020) on the packet to supply a packet drop signal (DROP), and perform a conditional limit operation and a conditional jump operation (3030).

Abstract: Metal-oxide-semiconductor (MOS) transistors with reduced subthreshold conduction, and methods of fabricating the same. Transistor gate structures are fabricated in these transistors of a shape and dimension as to overlap onto the active region from the interface between isolation dielectric structures and the transistor active areas. Minimum channel length conduction is therefore not available at the isolation-to-active interface, but rather the channel length along that interface is substantially lengthened, reducing off-state conduction.

Abstract: A network of processing devices includes a medium for low-latency interfaces for providing point-to-point connections between each of the processing devices. A switch within each processing device is arranged to facilitate communications in any combination between the processing resources and the local point-to-point interfaces within each processing device. A networking layer is provided above the low-latency interface stack, which facilitates re-use of software and exploits existing protocols for providing the point-to-point connections. Higher speeds are achieved for switching between the relatively low numbers of processor resources within each processing device, while low-latency point-to-point communications are achieved using the low-latency interfaces for accessing processor resources that are external to a processing device.

Abstract: A method of encoding samples in a digital signal is provided that includes receiving a frame of N samples of the digital signal, determining L possible distinct data values in the N samples, determining a reference data value in the L possible distinct data values and a coding order of L?1 remaining possible distinct data values, wherein each of the L?1 remaining possible distinct data values is mapped to a position in the coding order, decomposing the N samples into L?1 coding vectors based on the coding order, wherein each coding vector identifies the locations of one of the L?1 remaining possible distinct data values in the N samples, and encoding the L?1 coding vectors.

Abstract: A circuit is designed with a measurement circuit (432). The measurement circuit is coupled to receive a first input signal (903) from a first antenna (128) of a transmitter and coupled to receive a second input signal (913) from a second antenna (130) of the transmitter. Each of the first and second signals is transmitted at a first time. The measurement circuit produces an output signal corresponding to a magnitude of the first and second signals. A control circuit (430) is coupled to receive the output signal and a reference signal. The control circuit is arranged to produce a control signal at a second time in response to a comparison of the output signal and the reference signal.