Patents Assigned to Texas Instruments
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Patent number: 8598029Abstract: A semiconductor device, which comprises a workpiece with an outline and a plurality of contact pads and further an external part with a plurality of terminal pads. This part is spaced from the workpiece and the terminal pads are aligned with the workpiece contact pads, respectively. A reflow element interconnects each of the contact pads with its respective terminal pad. Thermoplastic material fills the space between the workpiece and the part; this material adheres to the workpiece, the part and the reflow elements. Further, the material has an outline substantially in line with the outline of the workpiece, and fills the space substantially without voids. Due to the thermoplastic character of the filling material, the finished device can be reworked, when the temperature range for reflowing the reflow elements is reached.Type: GrantFiled: May 8, 2012Date of Patent: December 3, 2013Assignee: Texas Instruments IncorporatedInventors: Masako Watanabe, Masazumi Amagai
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Patent number: 8598992Abstract: A RFID transponder includes a resonant circuit for providing a clock signal at a predetermined clock frequency, a self-calibration stage for calibrating the resonant circuit's current clock frequency towards the predetermined clock frequency. The self-calibration stage is adapted to compare a first clock frequency of the resonant circuit determined during an interrogation period, during which the resonant circuit is excited by an external RF signal, with a second clock frequency determined during a frequency maintenance period, during which the resonant circuit is excited internally through an oscillation maintenance circuit of the RFID transponder and to calibrate the resonant circuit towards the predetermined clock frequency based on the comparison result.Type: GrantFiled: October 30, 2008Date of Patent: December 3, 2013Assignee: Texas Instruments Deutschland GmbHInventor: Bernd Hertwig
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Patent number: 8601349Abstract: Apparatus and method for processing a physical layer protocol convergence (PLCP) header. In one embodiment, a wireless device includes a PLCP header processor. The PLCP header processor is configured to: process a physical layer header, process a check value based on the physical layer header, and process an error correction code based on the physical layer header and the check value. A concatenation of the physical layer header, check value, and error correction code the PLCP header processor is configured to process consists of a number of information bits that is an integer multiple of a number of information bits per symbol used to encode the PLCP header.Type: GrantFiled: August 29, 2011Date of Patent: December 3, 2013Assignee: Texas Instruments IncorporatedInventors: June Chul Roh, Anuj Batra, Srinath Hosur
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Patent number: 8598932Abstract: A clock divider is provided that is configured to divide a high speed input clock signal by an odd, even or fractional divide ratio. The input clock may have a clock cycle frequency of 1 GHz or higher, for example. The input clock signal is divided to produce an output clock signal by first receiving a divide factor value F representative of a divide ratio N, wherein the N may be an odd or an even integer. A fractional indicator indicates the divide ratio is N.5 when the fractional indicator is one and indicates the divide ratio is N when the fractional indicator is zero. F is set to 2(N.5)/2 for a fractional divide ratio and F is set to N/2 for an integer divide ratio. A count indicator is asserted every N/2 input clock cycles when N is even. The count indicator is asserted alternately N/2 input clock cycles and then 1+N/2 input clock cycles when N is odd.Type: GrantFiled: May 6, 2013Date of Patent: December 3, 2013Assignee: Texas Instruments IncorporatedInventors: Ramakrishnan Venkatasubramanian, Anthony Lell, Raguram Damodaran
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Patent number: 8601269Abstract: A system is provided that includes a first device and a second device. The second device is configured to communicate wirelessly with the first device. The first and second devices selectively reduce an operational range for communications before sharing a secret, the secret related to data encryption.Type: GrantFiled: June 23, 2006Date of Patent: December 3, 2013Assignee: Texas Instruments IncorporatedInventors: Anuj Batra, Srinivas Lingam
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Patent number: 8601040Abstract: A processor includes a shift overflow detector for rapidly detecting overflows that may result during execution of a shift instruction. Shift indication signals are generated in response to changes in logic state between adjacent pairs of bits of a received shift data word. A received shift amount is decoded to produce decoded shift signals that indicate an amount of shifting for the received shift data word. An overflow condition is detected in response to the generated shift indication signals and the decoded shift signals and an indication of the detected overflow condition is provided.Type: GrantFiled: September 27, 2010Date of Patent: December 3, 2013Assignee: Texas Instruments IncorporatedInventors: Timothy D. Anderson, Shriram D. Moharil
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Publication number: 20130314067Abstract: A low power DC-DC converter includes a converter stage coupled to an input node, and having a low side switch and a rectifier switch. A peak current detector senses a current at the low side switch and a zero current detector senses a current at the rectifier switch. It is configured to set the low side switch to a non-conductive state and the rectifier switch to a conductive state if the peak current detector detects a predetermined peak current. It is configured to set the rectifier switch to a non-conductive state if the zero current detector detects zero current at the rectifier switch. A time interval between subsequent current peaks is triggered by a charge comparator receiving an average current fed to the low side and rectifier switches from the input node and a reference current coupled to the charge comparator by a reference current source.Type: ApplicationFiled: May 25, 2012Publication date: November 28, 2013Applicant: Texas Instruments Deutschland GmbHInventors: Markus Matzberger, Konrad Wagensohner, Erich Bayer
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Publication number: 20130318413Abstract: Connection circuitry couples scan test port (STP) circuitry to test access port (TAP) circuitry. The connection circuitry has inputs connected to scan circuitry control output leads from the TAP circuitry, a select input lead, and a clock input lead. The connection circuitry has outputs connected to a scan enable (SE) input lead, a capture select (CS) input lead, and the scan clock (CK) input lead of the STP circuitry. The connection circuitry includes a multiplexer having a control input connected with a clock select lead from the TAP circuitry, an input connected with a functional clock lead, an input connected with the clock input lead, an input connected with a Clock-DR lead from the TAP circuitry, an OFF lead, and an output connected with the scan clock input lead.Type: ApplicationFiled: July 29, 2013Publication date: November 28, 2013Applicant: Texas Instruments IncorporatedInventor: Lee D. Whetsel
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Publication number: 20130318411Abstract: The disclosure describes a novel method and apparatus for providing expected data, mask data, and control signals to scan test architectures within a device using the falling edge of a test/scan clock. The signals are provided on device leads that are also used to provide signals to scan test architectures using the rising edge of the test/scan clock. According to the disclosure, device test leads serve to input different test signals on the rising and falling edge of the test/scan clock which reduces the number of interconnects between a tester and the device under test.Type: ApplicationFiled: July 29, 2013Publication date: November 28, 2013Applicant: Texas Instruments IncorporatedInventor: Lee D. Whetsel
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Publication number: 20130314114Abstract: A probe apparatus may include a plurality of probe pins attached to a probe head portion. Each of the probe pins may be independently movable relative to the probe head portion.Type: ApplicationFiled: May 24, 2012Publication date: November 28, 2013Applicant: Texas Instruments IncorporatedInventor: Hiroshi Miyazaki
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Publication number: 20130318506Abstract: At least some of the illustrative embodiments are a computer-readable medium storing a program that, when executed by a processor, causes the processor to obtain values indicative of a state of an operating context parameter during execution of a traced program on a target processor, and display an indication of a proportion of time during a trace period of the traced program that the target processor operated with the operating context parameter in a particular state.Type: ApplicationFiled: July 31, 2013Publication date: November 28, 2013Applicant: Texas Instruments IncorporatedInventors: Oliver P. Sohm, Brian Cruickshank
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Publication number: 20130318412Abstract: The disclosure provides a novel method and apparatus for inputting addresses to devices to select the device TAP for access. Further, the disclosure provides a novel method and apparatus for inputting addresses for selecting device TAPs and for inputting commands for commanding circuitry within the device. The inputting of addresses or the inputting of addresses and commands is initiated by a control bit input on TDI that is recognized during the Run Test/Idle, Pause-DR or Pause-IR TAP states.Type: ApplicationFiled: July 29, 2013Publication date: November 28, 2013Applicant: Texas Instruments IncorporatedInventor: Lee D. Whetsel
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Publication number: 20130316505Abstract: A method of fabricating gate level electrodes and interconnects in an integrated circuit, and an integrated circuit so fabricated, with improved process margin for the gate level interconnects of a width near the critical dimension. Off-axis illumination, as used in the photolithography of deep sub-micron critical dimension, is facilitated by the patterned features having a preferred orientation in a common direction, with a pitch constrained to within a relatively narrow range. Interconnects in that same gate level, for example “field poly” interconnects, that run parallel to an array of gate elements are placed within a specified distance range from the ends of the gate elements, or at a distance sufficient to allow sub-resolution assist features.Type: ApplicationFiled: July 26, 2013Publication date: November 28, 2013Applicant: Texas Instruments IncorporatedInventors: James Walter BLATCHFORD, JR., Yong Seok CHOI
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Publication number: 20130318409Abstract: A scan test architecture facilitates low power testing of semiconductor circuits by selectively dividing the serial scan paths into shorter sections. Multiplexers between the sections control connecting the sections into longer or shorted paths. Select and enable signals control the operation of the scan path sections. The output of each scan path passes through a multiplexer to compare circuits on the semiconductor substrate. The compare circuits also receive expected data and mask data. The compare circuits provide a fail flag output from the semiconductor substrate.Type: ApplicationFiled: July 29, 2013Publication date: November 28, 2013Applicant: Texas Instruments IncorporatedInventor: Lee D. Whetsel
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Patent number: 8593343Abstract: Embodiments of the invention provide a method of adjusting a bandwidth of receivers. A plurality of outputs from a correlator engine are combined. User dynamics are sensed. Bandwidth of one or more receivers are adjusted. By detecting when the user is stationary, the Doppler frequency estimation can be corrected or the SNR can be boosted more both of which lead to improved performance. The embodiments allow a receiver to process signals in when the signal level would otherwise be too low—for example indoors. The embodiments can improve performance when one or more satellites are temporarily blocked but one or more satellites are still being tracked.Type: GrantFiled: September 7, 2011Date of Patent: November 26, 2013Assignee: Texas Instruments IncorporatedInventors: Deric W. Waters, June Chul Roh, Sandeep Rao
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Patent number: 8593211Abstract: A half-bridge power circuit comprises a first gallium nitride field effect transistor (GaN FET); a first driver coupled to a gate of the first GaN FET; an anode of a capacitor coupled to an output of the driver and a source of the first GaN FET; a diode having a cathode coupled to the cathode of the capacitor; and a bootstrap capacitor clamp (BCC) controller, including: a field effect transistor (FET) coupled to an anode of the diode, and a comparator coupled to a gate of the FET, the comparator configured to receive as inputs: a) a signal representative of an input voltage (VDRV) applied to the FET; b) a ground; c) a boot signal representative of a voltage at the anode of the capacitor (Boot); and d) a signal representative of a voltage at the source of the first GaN FET (SW).Type: GrantFiled: March 16, 2012Date of Patent: November 26, 2013Assignee: Texas Instruments IncorporatedInventors: Hassan Pooya Forghani-Zadeh, Luis A. Huertas-Sanchez
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Patent number: 8593846Abstract: An analog floating gate circuit (10-3, 10-4) includes a first sense transistor (21, 3), a first storage capacitor (20, 5), and first (24, 4) and second (31A, 42) tunneling regions. Various portions of a first floating gate conductor (12, 2) form a floating gate of the first sense transistor, a floating first plate of the first storage capacitor (20, 5), a floating first plate of the first tunneling region, and a floating first plate of the second tunneling region, respectively. A second plate of the first storage capacitor is coupled to a first reference voltage (VREF, GND), and a second plate of the second tunneling region is coupled to a second reference voltage (VPROG/GND). Compensation circuitry (44-1, 44-2) is coupled to the first floating gate conductor, for compensating loss of trapped charge from the first floating gate conductor.Type: GrantFiled: August 17, 2011Date of Patent: November 26, 2013Assignee: Texas Instruments IncorporatedInventors: David A. Helsley, Allan T. Mitchell
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Patent number: 8593188Abstract: An improved charge pump based phase locked loop where the loop filter resistor noise is reduced by about an order is presented. The voltage controlled oscillator generates a clock signal, and this is input to the phase detector, which, compares the oscillator clock with the reference clock and using the Charge pump it generates a current output proportional to the phase difference. The loop filter converts this proportional current to a voltage and connects it to the oscillator input. The loop filter consists of a capacitor, resistor and the apparatus that bypasses most of the resistor noise.Type: GrantFiled: May 3, 2012Date of Patent: November 26, 2013Assignee: Texas Instruments IncorporatedInventor: Rajkumar Palwai
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Patent number: 8592307Abstract: A multi-layer TiN film with reduced tensile stress and discontinuous grain structure, and a method of fabricating the TiN film are disclosed. The TiN layers are formed by PVD or IMP in a nitrogen plasma. Tensile stress in a center layer of the film is reduced by increasing N2 gas flow to the nitrogen plasma, resulting in a Ti:N stoichiometry between 1:2.1 to 1:2.3. TiN films thicker than 40 nanometers without cracks are attained by the disclosed process.Type: GrantFiled: August 23, 2012Date of Patent: November 26, 2013Assignee: Texas Instruments IncorporatedInventors: Gregory Charles Herdt, Joseph W. Buckfeller
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Patent number: 8592902Abstract: Gate cross diffusion in a semiconductor structure is substantially reduced or eliminated by forming multiple n-type gate regions with different dopant concentrations and multiple p-type gate regions with different dopant concentrations so that the n-type gate region with the lowest dopant concentration touches the p-type gate region with the lowest dopant concentration.Type: GrantFiled: September 21, 2012Date of Patent: November 26, 2013Assignee: Texas Instrument IncorporatedInventor: Manoj Mehrotra
