Abstract: In accordance with at least some embodiments, a system comprises an access point and a station in communication with the access point. The station has at least two network technology subsystems subject to coexistence interference. The station selectively implements bounded Power Save (PS)-Polling (BPS) logic to handle communications between the station and the access point. The BPS logic operates to confine PS-Poll transmissions starts to one of two separate windows during a medium grant duration of the station.

Abstract: Image frames of a video stream are encoded with the aim of reducing flicker in the video stream when displayed. In one embodiment, the quantization parameter used to quantize an image frame is capped to be not greater than a quantization parameter used to quantize an immediately previous image frame. In another embodiment, the quantization step size used to quantize a macro-block of an image frame is computed based on the value of a quantization error of a co-located macro-block in an immediately previous image frame. In yet another embodiment, macro-block transform coefficients corresponding to high-frequency components are quantized using relatively higher quantization parameter values if the image frame is deemed to contain high activity. In yet another embodiment, flicker-prone macro-blocks of a source frame are replaced by corresponding best-match macro-blocks of a previous reconstructed frame, prior to being encoded.

Abstract: An integrated circuit containing CMOS gates and a counterdoped polysilicon gate material resistor which has a body region that is implanted concurrently with the NSD layers of the NMOS transistors of the CMOS gates and concurrently with the PSD layers of the PMOS transistors of the CMOS gates, and has a resistor silicide block layer over the body region which is formed of separate material from the sidewall spacers on the CMOS gates. A process of forming an integrated circuit containing CMOS gates and a counterdoped polysilicon gate material resistor which implants the body region of the resistor concurrently with the NSD layers of the NMOS transistors of the CMOS gates and concurrently with the PSD layers of the PMOS transistors of the CMOS gates, and forms a resistor silicide block layer over the body region of separate material from the sidewall spacers on the CMOS gates.

Abstract: A switched-capacitor circuit (10, 32 or 32A) samples a first signal (VIN+) onto a first capacitor (C1 or CIN1) by switching a top plate thereof via a summing conductor (13) to a first reference voltage (VSS) and switching a bottom plate thereof to the first signal. A second signal (VIN?) is sampled onto a second capacitor (C3 or CIN3) by switching a top plate thereof to the second signal and switching a bottom plate thereof to the first reference voltage. After the sampling, the top plate of the second capacitor is coupled to the top plate of the first capacitor. The bottom plate of the second capacitor is coupled to the first reference voltage.

Abstract: Enhancing search capacity of Global Navigation Satellite System (GNSS) receivers. A method for searching satellite signals in a receiver includes performing a plurality of searches sequentially. The method also includes storing a result from each search of the plurality of searches in a consecutive section of a memory. Further, the method includes detecting free sections in the memory. The method also includes concatenating the free sections in the memory to yield a concatenated free section. Moreover, the method includes allocating the concatenated free section for performing an additional search.

Abstract: A method for fabricating an integrated circuit includes the steps of: providing a substrate having a semiconductor surface; providing a hardmask material on the semiconductor surface. For at least one masking level of the integrated circuit: providing a mask pattern for the masking level partitioned into a first mask and at least one second mask, the first mask providing features in a first grid pattern and the at least one second mask providing features in a second grid pattern, wherein the first and the second grid pattern have respective features which interleave with one another over at least one area; applying a first photoresist layer with the first mask; exposing the first grid pattern using the first mask; developing the first photoresist layer; etching the hardmask material to transfer the first grid pattern in the surface of the substrate; removing the first photoresist layer.

Abstract: In an embodiment of the invention, an integrated circuit includes a pipelined memory array and a memory control circuit. The pipelined memory array contains a plurality of memory banks. Based partially on the read access time information of a memory bank, the memory control circuit is configured to select the number of clock cycles used during read latency.

Abstract: An integrated circuit containing an extended drain MOS transistor with deep semiconductor (SC) RESURF trenches in the drift region, in which each deep SC RESURF trench has a semiconductor RESURF layer at a sidewall of the trench contacting the drift region. The semiconductor RESURF layer has an opposite conductivity type from the drift region. The deep SC RESURF trenches have depth:width ratios of at least 5:1, and do not extend through a bottom surface of the drift region. A process of forming an integrated circuit with deep SC RESURF trenches in the drift region by etching undersized trenches and counterdoping the sidewall region to form the semiconductor RESURF layer. A process of forming an integrated circuit with deep SC RESURF trenches in the drift region by etching trenches and growing an epitaxial layer on the sidewall region to form the semiconductor RESURF layer.

Abstract: A power transistor module including a power transistor with a first common power node, and a split control node. A first clip is connected to a portion of a second power node so that current through a first control segment of the control node is directed through a first transistor portion and through the first clip. A second clip is connected to another portion of the second power node so that current through a second control segment is directed through a second transistor portion and through the second clip. A ratio of an area of the first transistor portion to a combined area of the first and second portions is 5 percent to 75 percent. A shunt is coupled in series to the first clip. The shunt may be directly electrically connected to the first portion of the power transistor.

Abstract: The present invention provides a single-electron transistor device 100. The device comprises a source 105 and drain 110 located over a substrate 115 and a quantum island 120 situated between the source and drain, to form tunnel junctions 125, 130 between the source and drain. The device further includes a fixed-gate electrode 135 located adjacent the quantum island 120. The fixed-gate electrode has a capacitance associated therewith that varies as a function of an applied voltage to the fixed-gate electrode. The present invention also includes a method of fabricating a single-electron device 300, and a transistor circuit 800 that include a single-electron device 810.

Abstract: Electrically erasable programmable “read-only” memory (EEPROM) cells in an integrated circuit, and formed by a single polysilicon level. The EEPROM cell consists of a coupling capacitor and a combined read transistor and tunneling capacitor. The capacitance of the coupling capacitor is much larger than that of the tunneling capacitor. In one embodiment, field oxide isolation structures isolate the devices from one another; a lightly-doped region at the source of the read transistor improves breakdown voltage performance. In another embodiment, trench isolation structures and a buried oxide layer surround the well regions at which the coupling capacitor and combined read transistor and tunneling capacitor are formed.

Abstract: Quantization for oversampled signals with an error minimization searches based upon clusters of possible sampling vectors where the clusters have minimal correlation and thereby decrease reconstruction error as a function of oversampling (redundancy) ratio.

Abstract: A silicon on insulator (SOI) multi-gate field effect transistor electrically Programmable Read-Only Memory (MuFET EPROM) includes a substrate having a dielectric surface. A first semiconducting region is in or on the dielectric surface. A source region, a drain region and a channel region interposed between the source and drain are formed in first semiconducting region. A gate dielectric layer is on the channel region. At least a second semiconducting region in or on the dielectric surface is spaced apart from the first semiconducting region. A first electrode layer comprises a first electrode portion including a transistor gate electrode and a control gate electrode electrically isolated from one another. The transistor gate overlies the channel region to form a transistor. The control gate extends to overlay a portion of the second semiconducting region.

Abstract: Motion detection in interlaced video fields, as useful in de-interlacing, includes spatial-temporal maximum filtering, temporal IIR filtering dependent upon spatial-temporal variance, and spatial variance dependent moving-still interpolation blending factor.

Abstract: An integrated circuit may be formed by forming a first interconnect pattern in a first plurality of parallel route tracks, and forming a second interconnect pattern in a second plurality of parallel route tracks, in which the second plurality of route tracks are alternated with the first plurality of route tracks. The first interconnect pattern includes a first lead pattern and the second interconnect pattern includes a second lead pattern, such that the route track containing the first lead pattern is immediately adjacent to the route track containing the second lead pattern. Metal interconnect lines are formed in the first interconnect pattern and the second interconnect pattern. A stretch crossconnect is formed in a vertical connecting level, such as a via or contact level, which electrically connects only the first lead and the second lead. The stretch crossconnect is formed concurrently with other vertical interconnect elements.

Abstract: A clock divider circuit. The clock divider receives m input clock signals each of the same frequency. Each input clock signal after the first has a phase offset of 2?/m from the previous input clock signal. The clock divider divides the frequency of the input clock signals by an integer of division K. The clock divider includes a counter that receives the first input clock signal and provides one or more count signals. The clock divider also includes m flip-flops, of which a first flip-flop receives the first input clock signal at its clock input and provides a first clock output signal. Each flip-flop after the first receives an input clock signal at its clock input and provides a clock output signal, each clock output signal after the first having a 2?K/m phase offset from the previous clock output signal.

Abstract: Traditionally, input source follower buffers for analog-to-digital converters (ADCs) lacked sufficiently high linearity. This was due in part to source follower buffers having to drive external capacitive loads by generally providing a signal current to the capacitive load. Here, a buffer is provided that includes a source follower buffer and other biasing circuitry (which provided the signal current). Thus, the overall linearity of the input circuitry (namely, the input buffer) is improved.

Abstract: A navigation system determines its usage mode. In some embodiments, a method comprises determining a usage mode of a navigation system based on at least one of an acceleration indicator, a speed indicator, and a magnet sensor. The usage mode is at least one of a pedestrian mode, a vehicular mode, an aerial mode, a train mode, and a marine mode. The method further comprises configuring a navigation subsystem based on the usage mode.

Abstract: Automatic gain control in a receiver. A method for controlling operating range of an analog-to-digital converter (ADC) by an automatic gain control circuit includes estimating a peak-to-average ratio corresponding to an analog signal from digital samples of the analog signal. The method includes determining a peak value corresponding to the analog signal based on the peak-to-average ratio. Further, the method includes maintaining magnitude of the analog signal at an input of the ADC and gain of the receiver based on the peak value.

Abstract: A method for signaling sample adaptive offset (SAO) band offset syntax elements in a video encoder is provided that includes receiving a plurality of band offset syntax elements, entropy encoding an absolute value of a magnitude of each band offset syntax element in a compressed video bit stream, and entropy encoding a sign of each non-zero band offset syntax element in the compressed video bit stream following the absolute values of the magnitudes.