Patents Assigned to Texas Instruments
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Patent number: 8589650Abstract: In a digital system with a processor coupled to a paged memory system, the memory system may be dynamically configured using a memory compaction manager in order to allow portions of the memory to be placed in a low power mode. As applications are executed by the processor, program instructions are copied from a non-volatile memory coupled to the processor into pages of the paged memory system under control of an operating system. Pages in the paged memory system that are not being used by the processor are periodically identified. The paged memory system is compacted by copying pages that are being used by the processor from a second region of the paged memory into a first region of the paged memory. The second region may be placed in a low power mode when it contains no pages that are being used by the processor.Type: GrantFiled: June 15, 2010Date of Patent: November 19, 2013Assignee: Texas Instruments IncorporatedInventors: Satoshi Yokoya, Philippe Gentric, Alain Michel Breton, Steven Charles Goss, Steven Richard Jahnke
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Patent number: 8589744Abstract: Plural scan test paths (401) are provided to reduce power consumed during testing such as combinational logic (101). A state machine (408) operates according to plural shift states (500) to control each scan path in capturing data from response outputs of the combinational logic and then shifting one bit at a time to reduce the capacitive and constant state power consumed by shifting the scan paths.Type: GrantFiled: October 17, 2012Date of Patent: November 19, 2013Assignee: Texas Instruments IncorporatedInventor: Lee D. Whetsel
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Patent number: 8587122Abstract: A solder joint between a trace (401) and an object (501). The trace having a solderable surface (503), a height (504), and a width (404), the trace including a bulge having a diameter (502) greater than the trace width, a surface area, and sidewalls, the sum of the bulge sidewall areas being no less than the bulge surface area. The object having a solderable surface (503), a diameter (502) greater than the trace width. One end of the object soldered to the bulge, wherein the solder (610, 611, 612) adheres to the bulge surface area and the bulge sidewall areas.Type: GrantFiled: August 29, 2011Date of Patent: November 19, 2013Assignee: Texas Instruments IncorporatedInventor: Kazuaki Mawatari
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Patent number: 8588275Abstract: The invention relates to an electronic device that includes a plurality of buffers and a phase locked loop. For each buffer a fractional divider is provided which is coupled to receive the output from the phase locked loop and configured to feed a divided output signal to a respective buffer. A spread spectrum clock control logic stage in the spread spectrum clock (SSC) is provided which is configured to individually adjust a value of the division of each fractional divider in order to individually and independently modulate the output signal of each fractional divider according to a spread spectrum modulation scheme.Type: GrantFiled: September 16, 2011Date of Patent: November 19, 2013Assignees: Texas Instruments Incorporated, Texas Instruments Deutschland GmbHInventors: Frank Gelhausen, Oliver Piepenstock, Mustafa U. Erdogan
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Patent number: 8589714Abstract: The disclosure describes a novel method and apparatus for allowing a controller to access a bus router using a communication occurring in response to one edge of a clock to select one or more devices for access using a communication occurring on the opposite edge of the clock. Additional embodiments are also provided and described in the disclosure.Type: GrantFiled: December 15, 2010Date of Patent: November 19, 2013Assignee: Texas Instruments IncorporatedInventor: Lee D. Whetsel
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Patent number: 8589839Abstract: Disclosed is an electrostatic discharge (ESD) protection validator, a method of validating ESD protection for an IC and an ESD validation system. In one embodiment, the ESD protection validator includes: (1) a circuit analyzer configured to compare component information of the IC with predefined ESD protection elements to identify ESD cells of the IC and (2) an ESD cell verifier configured to compare physical attributes associated with the identified ESD cells to ESD protection requirements and determine compliance therewith.Type: GrantFiled: July 21, 2009Date of Patent: November 19, 2013Assignee: Texas Instruments IncorporatedInventors: Gianluca Boselli, Jonathan S. Brodsky, John E. Kunz, Jr.
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Patent number: 8588536Abstract: A method of compressing digital image data is provided that includes, for each image data block in a plurality of image data blocks in the digital image data, transforming image data in the image data block to convert the image data to a low-frequency coefficient and a plurality of high-frequency coefficients, computing a predicted low-frequency coefficient for the image data block based on at least one neighboring image data block in the plurality of image data blocks, computing a residual low-frequency coefficient based on the predicted low-frequency coefficient and the low-frequency coefficient, quantizing the plurality of high-frequency coefficients, and entropy coding the residual low-frequency coefficient and the quantized high-frequency coefficients.Type: GrantFiled: February 10, 2011Date of Patent: November 19, 2013Assignee: Texas Instruments IncorporatedInventors: Salih Dikbas, Mehmet Umut Demircin, Minhua Zhou
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Patent number: 8589747Abstract: Scan distributor, collector, and controller circuitry connect to the functional inputs and outputs of core circuitry on integrated circuits to provide testing through those functional inputs and outputs. Multiplexer and demultiplexer circuits select between the scan circuitry and the functional inputs and outputs. The core circuitry can also be provided with built-in scan distributor, collector, and controller circuitry to avoid having to add it external of the core circuitry. With appropriately placed built-in scan distributor and collector circuits, connecting together the functional inputs and outputs of the core circuitry also connects together the scan distributor and collector circuitry in each core. This can provide a hierarchy of scan circuitry and reduce the need for separate test interconnects and multiplexers.Type: GrantFiled: May 9, 2013Date of Patent: November 19, 2013Assignee: Texas Instruments IncorporatedInventor: Lee D. Whetsel
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Patent number: 8587349Abstract: A clock divider circuit. The clock divider receives m input clock signals each of the same frequency. Each input clock signal after the first has a phase offset of 2?/m from the previous input clock signal. The clock divider divides the frequency of the input clock signals by an integer of division K. The clock divider includes a counter that receives the first input clock signal and provides one or more count signals. The clock divider also includes m flip-flops, of which a first flip-flop receives the first input clock signal at its clock input and provides a first clock output signal. Each flip-flop after the first receives an input clock signal at its clock input and provides a clock output signal, each clock output signal after the first having a 2?K/m phase offset from the previous clock output signal.Type: GrantFiled: May 21, 2013Date of Patent: November 19, 2013Assignee: Texas Instruments IncorporatedInventor: Rajesh Velayuthan
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Patent number: 8587967Abstract: One embodiment of the invention relates to a power apparatus. The power apparatus includes a power converter configured to convert an input voltage to an output voltage for providing power at an output thereof to which a load is connectable. The converter can include an isolation barrier configured to electrically isolate the output and the load from an input source that provides the input voltage. The system also includes a control loop that includes indirect sense circuitry configured to indirectly derive an indication of at least one of output current and output power of the converter. The control loop is configured to control output current or output power based on the indirectly derived indication of output current or output power, respectively.Type: GrantFiled: June 9, 2010Date of Patent: November 19, 2013Assignee: Texas Instruments IncorporatedInventor: Isaac Cohen
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Publication number: 20130301649Abstract: Embodiments of methods and systems for Carrier Sense Multiple Access with Collision Avoidance (CSMA/CA) with a random backoff time on a Power Line Communication (PLC) network are disclosed. The CSMA/CA method is independent of the algorithm used to update a contention window, so any contention window algorithm is supported. The PLC node runs an energy detection process first and then uses preamble detection only after energy detection is positive, or the node may run both energy detection and preamble detection simultaneously. Upon detection of a possible transmission on a PLC line due to energy detection, the PLC node will freeze a backoff counter decrementing process and will then wait for preamble detection to complete. If no energy is detected on the line, or if no preamble is detected after energy is sensed on the line, then the node will transmit is allowed by the contention window value.Type: ApplicationFiled: May 8, 2013Publication date: November 14, 2013Applicant: Texas Instruments IncorporatedInventors: Kumaran Vijayasankar, Ramanuja Vedantham, Tarkesh Pande
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Publication number: 20130305106Abstract: Various embodiments of methods and integrated circuits capable of generating a test mode control signal for a scan test through a scan chain (such as in an integrated circuit) are provided. The integrated circuit includes a test pattern detection block, a counter circuit, and a control circuit. The test pattern detection block is configured to receive a detection pattern and to detect a first pattern corresponding to a shift phase and a second pattern corresponding to a capture phase of a test pattern based on the detection pattern and to generate a trigger signal based upon the detection of the patterns. The control circuit generates and controls the test mode control signal based on the count states. The counter circuit is configured to generate one or more count states corresponding to one of the shift phase, the capture phase and the clock signal based on the detected pattern.Type: ApplicationFiled: May 14, 2012Publication date: November 14, 2013Applicant: Texas Instruments IncorporatedInventors: Rajesh Mittal, Puneet Sabbarwal, Prakash Narayanan, Rubin Ajit Parekhji
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Publication number: 20130300627Abstract: An apparatus is provided. First and second hybrid couplers are provided with each having a first port, a second port, a third port, a fourth port and with each being substantially curvilinear. The fourth ports of the first and second hybrid couplers are first and second isolation port that are mutually coupled. The first port of the first hybrid coupler is configured to carry a first portion of a differential signal, and the first port of the second hybrid coupler is configured to carry a second portion of the differential signal.Type: ApplicationFiled: May 8, 2012Publication date: November 14, 2013Applicant: Texas Instruments IncorporatedInventors: Swaminathan Sankaran, Nirmal C. Warke, Hassan Ali, Brad Kramer
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Publication number: 20130298827Abstract: A moveable dispenser assembly including is shown. The dispenser includes a reservoir having bonding adhesive therein including particles and a liquid carrier. The dispenser is moved to provide agitation to the dispenser for mixing the bonding adhesive into a homogeneous mixture of particles and the liquid carrier. An opening at an end of said dispenser dispenses the bonding adhesive onto a bonding location on the workpiece without removing the dispenser from the die attach apparatus. A one controller for sends a control signal that triggers moving of said moveable dispenser assembly for mixing said bonding adhesive before dispensing said volume of bonding adhesive onto said surface of said workpiece. The controller includes logic to control of movements such as oscillations to keep the bonding adhesive well mixed based on a comparing a parameter to be in a predetermined limit or range.Type: ApplicationFiled: July 19, 2013Publication date: November 14, 2013Applicant: Texas Instruments IncorporatedInventors: Frank Yu, Eric Hsieh, Kevin Jin
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Publication number: 20130305127Abstract: A method for encoding data words into a frame is provided. Input data words are received on a first bus having a first width. The input data words are buffered so as to output intermediate data words onto a second bus having a second width. A transcode bit is generated from the intermediate data words, and a set of parity bits is generated from the intermediate words using a syndrome generator, where the syndrome generator uses a number of bits that are equal to the second width. A frame is then generated from the intermediate data words and the set of parity bits and is output to a third bus having the first width.Type: ApplicationFiled: May 10, 2012Publication date: November 14, 2013Applicant: Texas Instruments IncorporatedInventors: Seuk B. Kim, Douglas E. Wente
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Publication number: 20130301453Abstract: A wireless device that tailors communications based on power parameters of the device. In one embodiment, a wireless device includes an energy source, a power monitor coupled to the energy source, a wireless transceiver, and a traffic controller coupled to the power monitor and the wireless transceiver. The power monitor is configured to measure a parameter of the energy source. The wireless transceiver is configured to wirelessly communicate via a wireless network. The traffic controller is configured to set length of packets to be transmitted based on the measured parameter of the energy source.Type: ApplicationFiled: May 10, 2013Publication date: November 14, 2013Applicant: Texas Instruments IncorporatedInventors: Ariton E. Xhafa, Soon-Hyeok Choi, Yanjun Sun, Leonardo William Estevez
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Publication number: 20130299966Abstract: A WSP die having a redistribution layer (“RDL”) with an RDL capture pad that has an RDL pad central axis RR and a RDL pad outer peripheral edge arranged about the RDL capture pad central axis RR and an under bump metal (UBM) pad positioned above the RDL capture pad. The UBM pad has a UBM pad central axis UU and a UBM pad outer peripheral edge arranged around the UBM pad central axis UU. The UBM pad central axis UU is laterally offset from the RDL pad central axis RR.Type: ApplicationFiled: May 10, 2012Publication date: November 14, 2013Applicant: Texas Instruments IncorporatedInventors: Anil KV Kumar, Gary Paul Morrison
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Publication number: 20130299967Abstract: A MP die with a redistribution layer (“RDL”) capture pad having at least one void therein and having an RDL capture pad outer peripheral edge and an under bump metal (“UBM”) pad positioned above the RDL capture pad and having a UBM pad outer peripheral edge positioned laterally inwardly of the RDL capture pad outer peripheral edge and positioned laterally outwardly of all the voids in the RDL capture pad.Type: ApplicationFiled: May 10, 2012Publication date: November 14, 2013Applicant: Texas Instruments IncorporatedInventors: Jeffrey David Daniels, Gary Paul Morrison
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Patent number: 8581629Abstract: An apparatus is provided. The apparatus includes an analog timing controller and a digital state machine. An input circuit in the digital state machine is configured to receive a plurality of analog input signals, and an analog event circuit is coupled to the analog timing circuit, the glitch filter, and the input circuit. The analog event circuit and input circuit are configured to generate a composite event signal from the analog input signals and by using the analog timing circuit. The glitch filter is configured to receive the composite event signal. A clock generator also is coupled to the glitch filter, wherein the clock generator is configured to generate an aperiodic clock signal. The aperiodic clock signal is configured to be a synchronous clock signal for the digital state machine.Type: GrantFiled: May 17, 2012Date of Patent: November 12, 2013Assignee: Texas Instruments IncorporatedInventors: Gary F. Chard, Scott A. Morrison, Susan A. Curtis, Daniel A. King
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Patent number: 8580663Abstract: A process for forming diffused region less than 20 nanometers deep with an average doping dose above 1014 cm?2 in an IC substrate, particularly LDD region in an MOS transistor, is disclosed. Dopants are implanted into a source dielectric layer using gas cluster ion beam (GCIB) implantation, molecular ion implantation or atomic ion implantation resulting in negligible damage in the IC substrate. A spike anneal or a laser anneal diffuses the implanted dopants into the IC substrate. The inventive process may also be applied to forming source and drain (S/D) regions. One source dielectric layer may be used for forming both NLDD and PLDD regions.Type: GrantFiled: August 25, 2011Date of Patent: November 12, 2013Assignee: Texas Instruments IncorporatedInventor: Amitabh Jain
