Patents Assigned to Texas Instruments
  • SYSTEM AND METHOD OF CLOCKING LOW SAMPLE RATE ANALOG TO DIGITAL CONVERTERS WHILE MINIMIZING LINEARITY ERRORS
    Publication number: 20130278452
    Abstract: A successive approximation register switched capacitor analog to digital converter utilizes a high frequency clock for controlling comparator reset switches and a clock distribution block to operate at lower sample rates. The successive approximation cycles are clocked with the high frequency clock so that the reset switches stay within the leakage limit irrespective of the sample rate but the end of conversion signal is delayed to mimic the slower sample rate.
    Type: Application
    Filed: April 20, 2012
    Publication date: October 24, 2013
    Applicant: Texas Instruments Incorporated
    Inventors: Haydar Bilhan, Maher Mahmoud Sarraj
  • ELECTRONIC DEVICE AND METHOD FOR ANALOG TO DIGITAL CONVERSION ACCORDING TO DELTA-SIGMA MODULATION USING DOUBLE SAMPLING
    Publication number: 20130278454
    Abstract: The modulator comprises a first and second integration stages, and a comparator, the first integration stage is fully differential having: an amplifier, sets of input sampling capacitors and feedback capacitors, and the first integration stage is configured to sample the analog input voltage on a set of input capacitors during a first portion of a clock cycle and on a set of input capacitors during a second portion of the clock cycle and to sample the feedback reference voltage on a set of feedback capacitors during the first portion of the clock cycle and on a set of feedback capacitors during the second portion of the clock cycle, and the first set of feedback capacitors and the second set of feedback capacitors are randomly selected out of the plurality of sets of feedback capacitors from cycle to cycle.
    Type: Application
    Filed: September 4, 2012
    Publication date: October 24, 2013
    Applicant: Texas Instrument Deutschland GmbH
    Inventors: Konstantin Schmid, Michael Reinhold, Frank Ohnhaeuser
  • Undetectable Combining of Nonaligned Concurrent Signals
    Publication number: 20130279700
    Abstract: The approach shown provides for an efficient implementation of time response, level response and frequency response alignment between two audio sources such as DAB and FM that may be time offset from each other by as much as 2 seconds, and produces an aurally undetectable transition between the sources. Computational load is significantly reduced over the approaches known in the prior art.
    Type: Application
    Filed: April 21, 2012
    Publication date: October 24, 2013
    Applicant: Texas Instruments Incorporated
    Inventors: John Elliott Whitecar, Trudy D Stetzler
  • METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR ENHANCING WHITE BALANCE OF AN IMAGE
    Publication number: 20130278792
    Abstract: In response to an image, a likelihood of flicker within the image is estimated. In response to the estimated likelihood, references are selected from among first and second sets of references. The first set of references are responsive to a first set of reference images captured under particular illumination. The second set of references are responsive to a second set of reference images captured under fluorescent illumination. In response to the selected references, one or more gains are generated for enhancing white balance of the image.
    Type: Application
    Filed: April 18, 2013
    Publication date: October 24, 2013
    Applicant: Texas Instruments Incorporated
    Inventor: Buyue Zhang
  • Clock phase compensation for adjusted voltage circuits
    Patent number: 8564351
    Abstract: Clock phases of clock signals in a dual clock tree are adjusted to compensate for variances in propagation delays of buffers in the clock tree. A first input clock and a second input clock are generated with the second input clock having a phase that is programmably shifted relative to the first input clock when the system is operating at a lowered operating voltage or different temperature, for example. The first and second input clocks are coupled to a dually clocked flip flop, each having a primary latch and a secondary latch. A composite clock signal is generated in response to the first input clock and the second input clock. For example, a first signal is latched in the primary latch in response to the composite clock signal and a second signal is latched in the secondary latch in response to the first input clock signal.
    Type: Grant
    Filed: August 1, 2011
    Date of Patent: October 22, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Hugh Thomas Mair, Jie Gu, Gordon Gammie
  • Method for implementing thermal management in a processor and/or apparatus and/or system employing the same
    Patent number: 8566621
    Abstract: A method for detecting temperature associated with a processor, results of the detecting being used for controlling power dissipation associated with the processor and/or apparatus and/or system employing the same.
    Type: Grant
    Filed: October 22, 2010
    Date of Patent: October 22, 2013
    Assignee: Texas Instruments Incorporated
    Inventor: LaVaughn F. Watts, Jr.
  • Ghosting artifact reduction in temporal noise filtering
    Patent number: 8564724
    Abstract: A method of noise filtering of a digital video sequence to reduce ghosting artifacts, the method including computing motion values for pixels in a frame of the digital video sequence based on a reference frame, computing blending factors for the pixels based on the motion values, generating filtered output pixel values by applying the blending factors to corresponding pixel values in the reference frame and the frame, wherein selected filtered output pixel values are converged toward corresponding pixel values in the frame to reduce ghosting artifacts, and outputting the filtered frame.
    Type: Grant
    Filed: April 4, 2010
    Date of Patent: October 22, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Wei Hong, Harmeet Singh
  • Generator and compactor adaptor for low power divided scan path
    Patent number: 8566659
    Abstract: A Scan-BIST architecture is adapted into a low power Scan-BIST architecture. A generator 102, compactor 106, and controller 110 remain the same as in the known art. The changes between the known art Scan-BIST architecture and the low power Scan-BIST architecture involve modification of the known scan path into scan path 502, to insert scan paths A 506, B 508 and C 510, and the insertion of an adaptor circuit 504 in the control path 114 between controller 110 and scan path 502.
    Type: Grant
    Filed: April 25, 2013
    Date of Patent: October 22, 2013
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • COMBINED PREDICTION WITH VARIABLE WEIGHT IN SCALABLE EXTENSION OF HEVC
    Publication number: 20130271664
    Abstract: Several systems and methods for filtering noise from a picture in a picture sequence associated with video data are disclosed. In an embodiment, the method includes accessing a plurality of pixel blocks associated with the picture and filtering noise from at least one pixel block from among the plurality of pixel blocks. The filtering of noise from a pixel block from among the at least one pixel block includes identifying pixel blocks corresponding to the pixel block in one or more reference pictures associated with the picture sequence. Each identified pixel block is associated with a cost value. One or more pixel blocks are selected from among the identified pixel blocks based on associated cost values. Weights are assigned to the selected one or more pixel blocks and set of filtered pixels for the pixel block is generated based on the weights.
    Type: Application
    Filed: April 5, 2013
    Publication date: October 17, 2013
    Applicant: Texas Instruments Incorporated
    Inventors: Manu Mathew, Shyam Jagannathan, Soyeb Noomohammed Nagori, Hrushikesh Tukaram Garud
  • Virtual Boundary Processing Simplification for Adaptive Loop Filtering (ALF) in Video Coding
    Publication number: 20130272624
    Abstract: Virtual boundary processing in adaptive loop filtering (ALF) requires that padded values be substituted for unavailable pixel rows outside the virtual boundaries. Methods and apparatus are provided for virtual boundary processing in ALF that allow the use of more actual pixel values for padding than in the prior art.
    Type: Application
    Filed: April 9, 2013
    Publication date: October 17, 2013
    Applicant: Texas Instruments Incorporated
    Inventor: Madhukar Budagavi
  • Reducing Context Coded and Bypass Coded Bins to Improve Context Adaptive Binary Arithmetic Coding (CABAC) Throughput
    Publication number: 20130272389
    Abstract: Techniques for context-adaptive binary arithmetic coding (CABAC) coding with a reduced number of context coded and/or bypass coded bins are provided. Rather than using only truncated unary binarization for the syntax element representing the delta quantization parameter and context coding all of the resulting bins as in the prior art, a different binarization is used and only part of the resulting bins are context coded, thus reducing the worst case number of context coded bins for this syntax element. Further, binarization techniques for the syntax element representing the remaining actual value of a transform coefficient are provided that restrict the maximum codeword length of this syntax element to 32 bits or less, thus reducing the number of bypass coded bins for this syntax element over the prior art.
    Type: Application
    Filed: April 14, 2013
    Publication date: October 17, 2013
    Applicant: Texas Instruments Incorporated
    Inventors: Vivienne Sze, Madhukar Budagavi
  • Color Component Checksum Computation in Video Coding
    Publication number: 20130272429
    Abstract: Checksum computation for video coding is provided that breaks the dependency between the color components of a picture in the prior art. More specifically, rather than computing a single checksum for a picture as in the prior art, a separate checksum is computed for each color component. Computing a separate checksum for each color component enables parallel computation of the component checksums. Methods are provided for computing three separate checksums after a picture is decoded. Methods are also provided for computing three separate checksums on a largest coding unit basis, thus allowing the checksums for a picture to be computed as the picture is being decoded.
    Type: Application
    Filed: April 16, 2013
    Publication date: October 17, 2013
    Applicant: Texas Instruments Incorporated
    Inventors: Ranga Ramanujam Srinivasan, Mihir Narendra Mody, Chaitanya Satish Ghone
  • METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR OPERATING A KEYBOARD
    Publication number: 20130271382
    Abstract: In response to a user selecting a key on a keyboard in a first manner, a first alphanumeric character is displayed on a display device. In response to the user selecting the key on the keyboard in a second manner, a virtual key of a diacritic is displayed on the display device. In response to the user selecting the virtual key of the diacritic on the display device, the diacritic is displayed at a location of a second alphanumeric character on the display device.
    Type: Application
    Filed: April 5, 2013
    Publication date: October 17, 2013
    Applicant: Texas Instruments Incorporated
    Inventor: Sajjad Mahmood Khan
  • Enhanced charger over voltage protection FET
    Patent number: 8559151
    Abstract: An integrated battery charger protection circuit incorporates a charge control power FET for series connection in the battery load current path from a DC supply input terminal to a controlled DC output terminal. The circuit has a gate drive input terminal connected to the gate of the charge control power FET and further includes protective circuitry adapted to disable the DC output terminal in a fault condition detected within the integrated circuit. The controlled DC output terminal and the gate drive input terminal are connectable to the external charge control host circuit the same way as corresponding terminals of a discrete power FET, in particular of p-channel type.
    Type: Grant
    Filed: June 9, 2009
    Date of Patent: October 15, 2013
    Assignee: Texas Instruments Deutschland GmbH
    Inventors: Ivo Huber, Andreas Fees
  • System and method for dynamically altering a color gamut
    Patent number: 8558771
    Abstract: System and method for dynamically altering a color gamut used in projection display systems. An embodiment comprises determining a dim color from colors used in representing an image, adjusting the dim color to increase an available display time for a non-dim color used to represent the image, adjusting the non-dim color using the available display time, and generating a color sequence based on the adjusted dim color and the adjusted non-dim color. The pixel intensities of a dim color are increased, permitting a shortening of the display time of the dim color. The newly freed display time can be reallocated to all colors to increase the amount of light used to display the image, thereby increasing image brightness or altering color point.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: October 15, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Todd Alan Clatanoff, Gregory S. Pettitt
  • Indium, carbon and halogen doping for PMOS transistors
    Patent number: 8558310
    Abstract: A method of forming an integrated circuit (IC) having at least one PMOS transistor includes performing PLDD implantation including co-implanting indium, carbon and a halogen, and a boron specie to establish source/drain extension regions in a substrate having a semiconductor surface on either side of a gate structure including a gate electrode on a gate dielectric formed on the semiconductor surface. Source and drain implantation is performed to establish source/drain regions, wherein the source/drain regions are distanced from the gate structure further than the source/drain extension regions. Source/drain annealing is performed after the source and drain implantation. The co-implants can be selectively provided to only core PMOS transistors, and the method can include a ultra high temperature anneal such as a laser anneal after the PLDD implantation.
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: October 15, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Mahalingam Nandakumar, Amitabh Jain
  • Integration scheme for changing crystal orientation in hybrid orientation technology (HOT) using direct silicon bonded (DSB) substrates
    Patent number: 8558318
    Abstract: Optimizing carrier mobilities in MOS transistors in CMOS ICs requires forming (100)-oriented silicon regions for NMOS and (110) regions for PMOS. Methods such as amorphization and templated recrystallization (ATR) have disadvantages for fabrication of deep submicron CMOS. This invention is a method of forming an integrated circuit (IC) which has (100) and (110)-oriented regions. The method forms a directly bonded silicon (DSB) layer of (110)-oriented silicon on a (100)-oriented substrate. The DSB layer is removed in the NMOS regions and a (100)-oriented silicon layer is formed by selective epitaxial growth (SEG), using the substrate as the seed layer. NMOS transistors are formed on the SEG layer, while PMOS transistors are formed on the DSB layer. An integrated circuit formed with the inventive method is also disclosed.
    Type: Grant
    Filed: January 14, 2011
    Date of Patent: October 15, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Angelo Pinto, Frank S Johnson, Benjamin P McKee, Shaofeng Yu
  • Electronic device and method for an amplifier with resistive feedback
    Patent number: 8558612
    Abstract: An electronic device comprising an amplifier having at least a first input transistor of a first doping type. A first transistor is coupled with a channel as a feedback path between an output of the amplifier and a control gate of the first input transistor forming an input of the amplifier. A diode-coupled second transistor is coupled with a channel between a first current source and the output of the amplifier wherein a control gate of the first transistor is coupled between the first current source and the diode-coupled second transistor and the first transistor is of a second doping type which is opposite to the first doping type of the first input transistor of the amplifier.
    Type: Grant
    Filed: March 1, 2012
    Date of Patent: October 15, 2013
    Assignee: Texas Instruments Deutschland GmbH
    Inventors: Carlo Peschke, Ernst Muellner
  • Low power retention random access memory with error correction on wake-up
    Patent number: 8560931
    Abstract: Solid-state random access memory including error correction capability applied to memory arrays entering and exiting a data retention mode. Error correction coding of the data to be retained is performed upon determining that a portion of the memory is to enter data retention mode; the parity bits (i.e., bits in addition to those required for storage of the payload) are stored in available memory cells within or external to the retention domain. Upon exit from retention mode, the code words are decoded to correct any errors, and the payload data are returned to the original cells. Error correction encoding and decoding is not performed in the normal operating mode.
    Type: Grant
    Filed: May 30, 2012
    Date of Patent: October 15, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Anand Seshadri, Wah Kit Loh
  • Low leakage capacitor for analog floating-gate integrated circuits
    Patent number: 8558296
    Abstract: An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is formed in a polycrystalline silicon gate level, and includes portions serving as a transistor gate electrode, a plate of a metal-to-poly storage capacitor, and a plate of poly-to-active tunneling capacitors. Silicide-block silicon dioxide blocks the formation of silicide cladding on the electrode, while other polysilicon structures in the integrated circuit are silicide-clad.
    Type: Grant
    Filed: March 23, 2011
    Date of Patent: October 15, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Imran Mahmood Khan, Allan T. Mitchell, Kaiping Liu