Abstract: A bidirectional electrostatic discharge (ESD) protection device includes a substrate having a topside semiconductor surface that includes a first silicon controlled rectifier (SCR) and a second SCR formed therein including a patterned p-buried layer (PBL) including a plurality of PBL regions. The first SCR includes a first and second n-channel remote drain MOS device each having a gate, a source within a p-body, and sharing a first merged drain. The second SCR includes a third and a fourth n-channel remote drain MOS device each having a gate, a source within a p-body, and sharing a second merged drain. The plurality of PBL regions are directly under at least a portion of the sources while being excluded from being directly under either of the merged drains.

Abstract: A Multi-Chip Module (MCM) package includes a substrate having a plurality of metal terminals and at least a first die attach area. An encapsulant is around the substrate including on at least a portion of the topside and at least a portion of the bottomside of the package. At least a first device including at least two device terminals is attached face up on the first die attach area. At least a second device including at least two device terminals is flip-chip attached and stacked on the first device. At least one of the first device and second device include a transistor. At least one metal clip is between the first device and second device including a plurality of clip portions isolated from one another connecting at least one device terminal of each of the first device and second device to respective metal terminals of the plurality of metal terminals.

Abstract: A method is provided. A first CMOS switch is deactivated while activating a second CMOS switch to cause the portion of the write signal to transition from a first direct current (DC) voltage to a first peak voltage. After a first interval, the second CMOS switch is deactivated while activating a third CMOS switch to cause the portion of the write signal to transition from the first peak voltage to a second DC voltage. After a second interval, the third CMOS switch is deactivated while activating a fourth CMOS switch to cause the portion of the write signal to transition from the second DC voltage to a second peak voltage After a third interval, the fourth CMOS switch is deactivated while activating the first CMOS switch to cause the portion of the write signal to transition from the second peak voltage to the first DC voltage.

Abstract: Apparatus and methods implement aggregation frames and allocation frames. The aggregation frames include a plurality of MSDUs or fragments thereof aggregated or otherwise combined together. An aggregation frame makes more efficient use of the wireless communication resources. The allocation frame defines a plurality of time intervals. The allocation frame specifies a pair of stations that are permitted to communicate with each other during each time interval as well as the antenna configuration to be used for the communication. This permits stations to know ahead of time when they are to communicate, with which other stations and the antenna configuration that should be used. A buffered traffic field can also be added to the frames to specify how much data remains to be transmitted following the current frame. This enables network traffic to be scheduled more effectively.

Abstract: An analog to digital converter includes leakage current correction circuitry to cancel leakage current injected by a reset switch employing a dummy PMOS switch with a shape factor substantially similar to that of the reset switch. An operational amplifier replicates the voltage of the comparator sense input node to the drain of the dummy transistor to create the same operating point as the reset switch. The resulting leakage current is then repeated and fed back to the node to cancel the offending leakage current.

Abstract: System and method for signaling control information in a multi-carrier communications system to transmit data. A preferred embodiment comprises demodulating a first carrier that is used for transmitting a control channel transmission, determining a second carrier that is used for transmitting a data channel transmission based upon the demodulated control channel transmission, and demodulating the second carrier to obtain the data channel transmission. Additionally, designs for multi-carrier receivers are provided.

Abstract: A computer program that is embodied on a storage medium for execution on a processor is provided. With this computer program, A current cost is calculated for each transition on a bus having a predetermined width for a functional circuit so as to form a transition cost matrix. Then, a predetermined number of the lowest cost transitions for from the transition cost matrix is determined so as to generate a probability transition matrix. The product of the probability transition matrix and the transition cost matrix can be iteratively determined, while also updating the probability transition matrix until the probability transition matrix converges.

Abstract: The objective of this invention is to provide a solid-state image pickup device and its driving method that has a minimum circuit area and a wide dynamic range. The invention includes: a sensor array SA; a memory M; and a signal determination circuit DC. The sensor array has plural pixels in an array integrated on a semiconductor substrate. Each pixel sequentially outputs a first signal and a second signal. The memory M is connected to each column of pixels array and stores the first signal or the second signal. The signal determination circuit DC outputs signal (SS) such that it works as follows: when the first signal is input to memory M from the pixel, the signal determination circuit DC determines whether the first signal can be used. If so, the first signal is selected and the second signal is discarded and is not output to memory M. When the second signal is selected, the second signal is uploaded to memory M.

Abstract: A processor includes a two's complement arithmetic unit that reduces a level of complexity in the critical path by eliminating the addition of the “1” to the carry in of the two's complement arithmetic unit. To execute a subtraction instruction using two's complement arithmetic, the subtraction as disclosed herein is performed in accordance with the identity “A?B=not (not (A)+B),” where A is a first operand and B is a second operand that is to be subtracted from A. Accordingly, the addition of the “1” term into the carry in is eliminated, and reduces a level of complexity that would otherwise slow down and/or limit the speed at which a subtraction instruction can be performed.

Abstract: The disclosure describes a novel method and apparatus for improving the operation of a TAP architecture in a device through the use of Command signal inputs to the TAP architecture. In response to a Command signal input, the TAP architecture can perform streamlined and uninterrupted Update, Capture and Shift operation cycles to a target circuit in the device or streamlined and uninterrupted capture and shift operation cycles to a target circuit in the device. The Command signals can be input to the TAP architecture via the devices dedicated TMS or TDI inputs or via a separate CMD input to the device.

Abstract: A method of reading a memory cell. The method includes the step of connecting (708) a reference voltage generator (600) to a first bitline (/BL). The first bitline is charged to a reference voltage (VREF) from the reference voltage generator. The reference voltage generator is disconnected (RFWL_A/B low at t4, FIG. 10B) from the first bitline. A signal voltage (PL high at t4, FIG. 10B) from the memory cell is applied to a second bitline (BL) after the step of disconnecting. A difference voltage between the first and second bitlines is amplified (SAEN high at t7, FIGS. 8A and 10B).

Abstract: This invention targets improvement in CMOS sensors using a multiplexed read-out architecture in which pixels are output at the pixel VN level instead of the line/reference amplifier level. The pixel signal voltage VN and offset voltage VNS are read sequentially, eliminating the differential structure. Interference rejection, usually achieved by a differential signal, is obtained by using a CDS (Correlated Double Sampler) in the same way as in the prior art.

Abstract: Various exemplary embodiments provide components, devices, and methods of semiconductor packaging. The disclosed packaging component can include a mold material disposed around a lead frame and at least an integrated circuit (IC), wherein the IC is electrically connected with one side of the lead frame. The opposite side of the lead frame including, for example, lead segments, can be exposed from the mold material. A variety of other components, devices, and packages can then be assembled, e.g., over the disclosed packaging component, through the exposed regions so as to improve packaging densities.

Abstract: A method is provided that includes performing a free placement of a system design comprising a plurality of power domains, wherein the power domains are not constrained to physical regions, assigning a physical region to each of the power domains based on the free placement of cells in the power domains, performing a soft cluster placement of the system design with each power domain and corresponding physical region defined as a soft cluster, refining at least one physical region based on the soft cluster placement, redefining cells in at least one power domain based on the soft cluster placement of the cells and the corresponding physical region, and performing a hard cluster placement of the system design with each power domain and corresponding physical region defined as a hard cluster to generate final power domains.

Abstract: The objective of this invention is to provide a photodiode which has high sensitivity even to light with a wavelength in the blue region while maintaining the high-frequency characterstics. The n type second semiconductor layer (13) containing an n type electroconductive impurity at a low concentration is formed directly or via an intrinsic semiconductor layer (11) on the p type first semiconductor layer (10). The third semiconductor layer (20) containing an n type electroconductive impurity at a medium concentration is formed shallower than said second semiconductor layer (13) in its main plane. The fourth semiconductor layer (21) containing an n type electroconductive impurity at a high concentration is formed shallower than said third semiconductor layer (20) in the main plane of the third semiconductor layer (20).

Abstract: A method of fabricating gate level electrodes and interconnects in an integrated circuit, and an integrated circuit so fabricated, with improved process margin for the gate level interconnects of a width near the critical dimension. Off-axis illumination, as used in the photolithography of deep sub-micron critical dimension, is facilitated by the patterned features having a preferred orientation in a common direction, with a pitch constrained to within a relatively narrow range. Interconnects in that same gate level, for example “field poly” interconnects, that run parallel to an array of gate elements are placed within a specified distance range from the ends of the gate elements, or at a distance sufficient to allow sub-resolution assist features.

Abstract: A tunable depletion diode is provided. Within this depletion diode, there is a depletion mode transistor that is coupled to the anode terminal at its gate and the cathode terminal at its drain. A diode is coupled between the source of the depletion mode transistor and the anode terminal, and a variable capacitor is coupled between the source of the depletion mode transistor and the anode terminal, where the capacitance of the variable capacitor is controls the reverse recovery time of the tunable depletion diode.

Abstract: System and method for wirelessly providing multimedia. A system includes a headset and a wireless communications device. The wireless communications device controls the operation of the headset with transmissions over a first wireless network. The headset includes a first ear piece, a second ear piece, and a connecting piece. The first ear piece has a first speaker, a first network interface to send and receive transmissions over the first wireless network, a second network interface to receive transmissions over a second wireless network, and a connecting piece. The connecting piece is coupled between the first ear piece and the second ear piece. The connecting piece includes a wire to electrically couple the second ear piece, the first ear piece, and the second network interface and to receive transmissions over the second wireless network. The wire may be made to any length since it may be embedded inside the connecting piece.

Abstract: Transmitting a acknowledge/not acknowledge (ACK/NACK) response in a wireless cellular network by mapping the data value into a cyclic shifted version of a reference signal. A subframe is formed with a plurality of symbols with certain symbols designated as reference signal (RS) symbols. The receiver and transmitter both know when an ACK/NACK response is expected. If an ACK/NACK response is not expected, then an RS is inserted in the duration of symbols designated as RS symbols. If an ACK/NACK response is expected, then the ACK/NACK response is embedded in one or more of the symbols designated as RS symbols. The subframe is transmitted to a receiver, and the receiver can determine the ACK/NACK value in the RS symbol, if present, and also use the RS symbol for coherent demodulation of a CQI (channel quality indicator) or data.

Abstract: A test controller applies test stimulus signals to the input pads of plural die on a wafer in parallel. The test controller also applies encoded test response signals to the output pads of the plural die in parallel. The encoded test response signals are decoded on the die and compared to core test response signals produced from applying the test stimulus signals to core circuits on the die. The comparison produces pass/fail signals that are loaded in to scan cells of an IEEE 1149.1 scan path. The pass/fail signals then may be scanned out of the die to determine the results of the test.