Abstract: A circuit has a digital to analog (DA) resistance ladder having an analog output; a capacitor coupled to the analog output; a first resistance coupled from the capacitor to ground; and a switch coupled to the capacitor in parallel to the resistor, wherein the switch, when closed, has a second resistance, and the first resistance is greater than the second resistance.

Abstract: A photovoltaic cell is provided as a composite unit together with elements of an integrated circuit on a common substrate. In a described embodiment, connections are established between a multiple photovoltaic cell portion and a circuitry portion of an integrated structure to enable self-powering of the circuitry portion by the multiple photovoltaic cell portion.

Abstract: A CVD showerhead that includes a circular inner showerhead and at least one outer ring showerhead. At least two process gas delivery tubes are coupled to each showerhead. Also, a dual showerhead that includes a circular inner showerhead and at least one outer ring showerhead where each showerhead is coupled to oxygen plus a gas mixture of lead, zirconium, and titanium organometallics. A method of depositing a CVD thin film on a wafer. Also, a method of depositing a PZT thin film on a wafer.

Abstract: A semiconductor device includes a semiconductor substrate, a first p-channel laterally diffused metal oxide semiconductor (LDMOS) transistor formed over the semiconductor substrate and additional p-channel LDMOS transistors formed over the semiconductor substrate. First drain and gate electrodes are formed over the substrate and are coupled to the first LDMOS transistor. Additional drain and gate electrodes are formed over the substrate and are coupled to the second LDMOS transistor. A common source electrode for the first and second LDMOS transistors is also formed over the substrate.

Abstract: A system and circuit for simulating gate-to-drain breakdown in an N-channel field effect transistor (NFET). In one embodiment, a simulation circuit includes a primary field effect transistor (FET), a first depletion mode FET and a second depletion mode FET. The first depletion mode FET and the second depletion mode FET are connected between a gate and a drain of the primary FET. A gate and a drain of the first depletion mode FET are connected to the gate of the primary FET. A gate and a drain of the second depletion mode FET are connected to the drain of the primary FET.

Abstract: A successive approximation register switched capacitor analog to digital converter utilizes a high frequency clock for controlling comparator reset switches and a clock distribution block to operate at lower sample rates. The successive approximation cycles are clocked with the high frequency clock so that the reset switches stay within the leakage limit irrespective of the sample rate but the end of conversion signal is delayed to mimic the slower sample rate.

Abstract: A method includes receiving a first plurality of symbols comprising complex portions. The method further includes applying conjugate symmetry to the first plurality of symbols, producing a second plurality of symbols comprising no complex portions. The method further includes transforming the second plurality of symbols using an inverse fast Fourier transform, producing a third plurality of symbols. The method further includes interpolating the third plurality of symbols, generating a short training field comprising at least one real portion of the third plurality of symbols, generating a long training field comprising at least one real portion of the third plurality of symbols, and transmitting the short training field and long training field in a WPAN.

Abstract: An electronic device is provided for controlling a current. The electronic device includes a first MOS transistor coupled with a gate to a common gate node, with a source to ground and with a drain to a pin so as to receive from the pin a current to be controlled. There is a second MOS transistor coupled with a gate to the common gate node, with a source to ground and with a drain so as to receive a reference current controlled by a control loop. There is a first resistor coupled between the common gate node and ground.

Abstract: Power optimization in a medical implant based system. A method includes receiving a portion of a signal by a first transceiver. The method further includes determining, from the portion of the signal, a time duration after which a subsequent portion of the signal will be transmitted. The subsequent portion is transmitted at end of the portion. The method also includes entering into an inactive state for the time duration.

Abstract: A method of simulating an integrated circuit device under test (DUT) is provided, wherein the DUT includes a plurality of terminals. For each terminal of the DUT, a probe pulse is applied to the terminal and a reaction is recorded at the terminal and each of the other terminals to obtain values representative of reactive tails for the terminal. For each terminal, the values representative of the reactive tails obtained for the terminal are stored as an entry of a look-up table. Each entry includes n+x fields, wherein n represents a number of arguments in the entry and x represents a number of functions in the entry. For each terminal, a signal value at a selected time step is calculated.

Abstract: Low density parity check (LDPC) decoding can be mapped to a class of DSP instructions called MINST. The MINST class of instructions significantly enhance the efficiency of LDPC decoding by merging several of the functions required by LDPC decoders into a single MINST instruction. This invention is an efficient implementation of the MINST class of instructions using a configurable three input arithmetic logic unit. The carry output results of the three input arithmetic logic unit enable permit boundary decisions in a range determination required by the MINST instruction. The preferred embodiment employs 2's complement arithmetic and carry-save adder logic. This invention allows reuse of hardware required to implement MAX* functions in LDPC functions.

Abstract: A method for semiconductor processing is provided wherein a workpiece having an underlying body and a plurality of features extending therefrom, is provided. A first set of the plurality of features extend from the underlying body to a first plane, and a second set of the plurality features extend from the underlying body to a second plane. A protection layer overlies each of the plurality of features and an isolation layer overlies the underlying body and protection layer, wherein the isolation has a non-uniform first oxide density associated therewith. The isolation layer anisotropically etched based on a predetermined pattern, and then isotropically etched, wherein a second oxide density of the isolation layer is substantially uniform across the workpiece. The predetermined pattern is based, at least in part, on a desired oxide density, a location and extension of the plurality of features to the first and second planes.

Abstract: A digital power supply and power supply controller are presented, including a voltage control loop and a current control loop, with a controller for pulse width modulating a switching power supply according to a voltage control loop duty cycle output or a current control loop duty cycle output, in which the controller selectively presets the voltage control loop duty cycle output to a predetermined value before switching from current loop control to voltage loop control and/or inhibits increase in a voltage loop integrator value during current loop control to mitigate voltage overshoot.

Abstract: Apparatus and methods implement aggregation frames and allocation frames. The aggregation frames include a plurality of MSDUs or fragments thereof aggregated or otherwise combined together. An aggregation frame makes more efficient use of the wireless communication resources. The allocation frame defines a plurality of time intervals. The allocation frame specifies a pair of stations that are permitted to communicate with each other during each time interval as well as the antenna configuration to be used for the communication. This permits stations to know ahead of time when they are to communicate, with which other stations and the antenna configuration that should be used. A buffered traffic field can also be added to the frames to specify how much data remains to be transmitted following the current frame. This enables network traffic to be scheduled more effectively.

Abstract: A method of operating a wireless communication system (FIG. 4) is disclosed. The method includes receiving a plurality of reference signals from a respective plurality of transceivers (402). Each, of the plurality of reference signals is measured to produce a respective plurality of channel state information (CSI) measurements (404). An aggregated channel quality indicator (CQI) is calculated from measuring the plurality of reference signals (406). The aggregated CQI is transmitted to at least one transceiver of the respective plurality of transceivers (408).

Abstract: An apparatus is provided. A first switch is coupled between first and third nodes in an H-bridge. A second switch is coupled between first and fourth nodes in the H-bridge. A third switch is coupled between the second and third nodes. A fourth switch is coupled between second and fourth nodes in the H-bridge. A first source-follower is coupled to the first node of the H-bridge and the first supply rail, and the first source-follower is configured to receive a first reference signal. A second source-follower is coupled to the second node of the H-bridge and the second supply rail, and the second source-follower is configured to receive a second reference signal.

Abstract: Multiplier circuitry includes first multiplier circuit including a first transistor having an emitter coupled to a first conductor, a base coupled to a second conductor, and a collector coupled to a third conductor, a second transistor having an emitter coupled to the first conductor, a base coupled to a fourth conductor, and a collector coupled to a fifth conductor, a third transistor having an emitter coupled to the second conductor and a base and collector coupled to a supply voltage, and a fourth transistor having an emitter coupled to the fourth conductor and a base and collector coupled to the supply voltage. Chopper includes a first switch to provide a chopped differential signal between the second and fourth conductors and a second switch for un-chopping a first differential output signal produced between the third and fifth conductors to provide an un-chopped differential output signal between the third and fifth conductors.

Abstract: A computer program for generating a layout for a ferroelectric random access memory (FRAM) that is embodied on a non-transitory storage medium and executable by a processor is provided. FRAM specifications are received, and an FRAM floorplan and design rules are retrieved from the non-transitory storage medium. The layout for the FRAM based on the FRAM specifications and design rules is then assembled.

Abstract: In an embodiment of the invention, a method of fabricating a floating-gate PMOSFET (p-type metal-oxide semiconductor field-effect transistor) is disclosed. A silicide blocking layer (e.g. oxide, nitride) is used not only to block areas from being silicided but to also form an insulator on top of a poly-silicon gate. The insulator along with a top electrode (control gate) forms a capacitor on top of the poly-silicon gate. The poly-silicon gate also serves at the bottom electrode of the capacitor. The capacitor can then be used to capacitively couple charge to the poly-silicon gate. Because the poly-silicon gate is surrounded by insulating material, the charge coupled to the poly-silicon gate may be stored for a long period of time after a programming operation.

Abstract: A method includes searching a plurality of lines of a log file for a violation of a defined condition; creating a database of all discovered violations; converting the database of all discovered to a list of output violations grouped by master; and producing a condensed summary of error messages, the producing including: searching for a selected error message; extracting a single instance or error message and load into a master log file; searching for all other examples at all levels of a hierarchical output of the list; writing a count of instances of the violation messages to the master log file; and presenting a single instance of the violations, and the count of that violation.