Abstract: This invention is a preprocessor apparatus and method algorithm facilitating black bar detection in video frames or fields. The preprocessing marks a sharp discontinuity between pixels a predetermined distance apart on each line. On first detection of this discontinuity the location and pixel value is stored. The location and pixel value is also stored for the last discontinuity in the line. This data enables software to detect top horizontal bars, bottom horizontal bars, left vertical bars and right vertical bars.

Abstract: A method of register allocation in complier using a computer instruction set having tiered instructions that accesses differing numbers of registers makes a first preliminary register allocation attempt using an initially specified register set for each instruction. If this fails, the method identifies instructions having an initially specified limited register having a variable not register allocatable. The method makes a second preliminary register allocation attempt except using a less restrictive register set for the identified instructions. This method employs a next less restrictive register set and re-attempts preliminary register allocations for instructions with more than two levels of register restriction.

Abstract: In accordance with at least some embodiments, a system includes an access point and a station in communication with the access point. The station selectively implements adaptive periodic Power-Save (APPS)-Polling logic for communications between the station and the access point. The APPS-Polling logic is configured to determine a timer value for periodic PS-Polling by monitoring a periodicity of arrival packets for at least a threshold amount of time.

Abstract: A system and method for determining a position of a mobile wireless device using wireless local area network access points (APs). In one embodiment, a mobile wireless device includes an AP positioning system configured to estimate a position of the device based on locations of APs disposed about the device. The AP positioning system is configured to: 1) access an AP database; and 2) provide, to the database, one or more medium access controller (MAC) addresses and an area of interest value. The AP positioning system is also configured to retrieve, from the database: 1) location information for each AP having a provided MAC address, or located within the area of interest; and 2) at least one of: signal parameters for the APs nearby the device, a geographic area within which each MAC address can be received, and an indication of a scan type to used for identifying APs.

Abstract: The invention relates to a method of manufacturing an integrated circuit. An electrically resistive layer of a material for serving as a thin film resistor (TFR) is deposited. A first electrically insulating layer is deposited on the electrically resistive layer of the TFR. An electrically conductive layer of an electrically conductive material is deposited. An area is left without the conductive layer and the area overlaps the electrically resistive layer of the TFR. A second electrically insulating layer is deposited on top of the conductive layer. A first VIA opening is etched through the second insulating layer, the area without the conductive layer adjacent to the electrically conductive layer and through the first insulating layer down to the electrically resistive layer of the TFR. A conductive material is deposited in the first VIA opening so as to electrically connect the conductive layer and the electrically resistive layer of the TFR.

Abstract: In a first embodiment a Test Access Port (TAP) of IEEE standard 1149.1 is allowed to commandeer control from a Wrapper Serial Port (WSP) of IEEE standard P1500 such that the P1500 architecture, normally controlled by the WSP, is rendered controllable by the TAP. In a second embodiment (1) the TAP and WSP based architectures are merged together such that the sharing of the previously described architectural elements are possible, and (2) the TAP and WSP test interfaces are merged into a single optimized test interface that is operable to perform all operations of each separate test interface. One approach provides for the TAP to maintain access and control of the TAP instruction register, but provides for a selected data register to be accessed and controlled by either the TAP+ATC (Auxiliary Test Control bus) or by the discrete CaptureDR, UpdateDR, TransferDR, ShiftDR, and ClockDR WSP data register control signals.

Abstract: A test architecture accesses IP core test wrappers within an IC using a Link Instruction Register (LIR). An IEEE P1500 standard is in development for providing test access to these individual cores via a test structure called a wrapper. The wrapper resides at the boundary of the core and provides a way to test the core and the interconnections between cores. The test architecture enables each of the plural wrappers in the IC, including wrappers in cores embedded within other cores, with separate enable signals.

Abstract: A process and apparatus provide a JTAG TAP controller (302) to access a JTAG TAP domain (106) of a device using a reduced pin count, high speed DDR interface (202). The access is accomplished by combining the separate TDI and TMS signals from the TAP controller into a single signal and communicating the TDI and TMS signals of the single signal on the rising and falling edges of the TCK driving the DDR interface. The TAP domain may be coupled to the TAP controller in a point to point fashion or in an addressable bus fashion. The access to the TAP domain may be used for JTAG based device testing, debugging, programming, or other type of JTAG based operation.

Abstract: The disclosure describes a novel method and apparatuses for allowing a controller to select and access different types of access ports in a device. The selecting and accessing of the access ports is achieved using only the dedicated TDI, TMS, TCK, and TDO signal terminals of the device. The selecting and accessing of device access ports can be achieved when a single device is connected to the controller, when multiple devices are placed in a daisy-chain arrangement and connected to the controller, or when multiple devices are placed in a addressable parallel arrangement and connected to the controller. Additional embodiments are also provided and described in the disclosure.

Abstract: A clock divider circuit. The clock divider receives m input clock signals each of the same frequency. Each input clock signal after the first has a phase offset of 2?/m from the previous input clock signal. The clock divider divides the frequency of the input clock signals by an integer of division K. The clock divider includes a counter that receives the first input clock signal and provides one or more count signals. The clock divider also includes m flip-flops, of which a first flip-flop receives the first input clock signal at its clock input and provides a first clock output signal. Each flip-flop after the first receives an input clock signal at its clock input and provides a clock output signal, each clock output signal after the first having a 2?K/m phase offset from the previous clock output signal.

Abstract: Embodiments of methods and systems are presented for generating PHY frames with multiple Reed-Solomon encoded blocks in PLC networks. In one embodiment, a MAC layer divides a data frame from a higher level into data blocks. The MAC layer may add a MAC header and/or an error-detection code to each data block. The MAC layer then passes the data blocks to a PHY layer to be individually Reed-Solomon encoded and combined into a single PHY frame for transmission on a PLC network. In other embodiments, the MAC layer passes a single data frame to the PHY layer, which divides the MAC data frame into segments to be individually Reed-Solomon encoded. The individual Reed-Solomon encoded segments are combined into a single PHY frame for transmission on a PLC network.

Abstract: Timely testing of die on wafer reduces the cost to manufacture ICs. This disclosure describes a die test structure and process to reduce test time by adding test pads on the top surface of the die. The added test pads allow a tester to probe and test more circuits within the die simultaneously. Also, the added test pads contribute to a reduction in the amount of test wiring overhead traditionally required to access and test circuits within a die, thus reducing die size.

Abstract: A method of computational lithography includes collecting a critical dimension (CD) data set including CD data from printing a test structure including a set of gratings which provide a plurality of feature types including different ratios of line width to space width, where the printing includes a range of different focus values. The CD data is weighted to form a weighted CD data set using a weighting algorithm (WA) that assigns cost weights to the CD data based its feature type and its magnitude of CD variation with respect to a CD value for its feature type at a nominal focus (nominal CD). The WA algorithm reduces a value of the cost weight as the magnitude of variation increases. At least one imaging parameter is extracted from the weighted CD data set. A computational lithography model is automatically calibrated using the imaging parameter(s).

Abstract: A method of protecting through substrate via (TSV) die from bonding damage includes providing a substrate including a plurality of TSV die having a topside including active circuitry, a bottomside, and a plurality of TSVs that include an inner metal core that reaches from the topside to protruding TSV tips that extend out from the bottomside. A protective layer is formed on or applied to the bottomside of the TSV die including between and over the protruding TSV tips. The TSV die is bonded with its topside down onto a workpiece having a workpiece surface and its bottomside up and in contact with a bond head. The protective layer reduces damage from the bonding process including warpage of the TSV die by preventing the bond head from making direct contact to the protruding TSV tips.

Abstract: A method of computational lithography includes collecting inline post-develop resist critical dimension (CD) data obtained from printing a test structure having resist on a substrate having a layer thereon using a mask including a set of gratings having main features and resolution assist features (RAFs) in proximity to the main features. The RAFs include a size range so that a lithography system used for the printing prints some of the RAFs, while some of the RAFs do not print. A plurality of resist kernels are determined from the post-develop resist CD data including a non-Gaussian developer etching kernel which represents a developer used for the printing and a Gaussian kernel. A resist model is generated which provides a resist image contour from an aerial image contour and the plurality of resist kernels.

Abstract: The peripheral circuitry (350, 360, ESD, BH) of an integrated circuit die on a wafer is tested without physically contacting the bond pads of the die.

Abstract: A clock divider circuit. The clock divider receives m input clock signals each of the same frequency. Each input clock signal after the first has a phase offset of 2?/m from the previous input clock signal. The clock divider divides the frequency of the input clock signals by an integer of division K. The clock divider includes a counter that receives the first input clock signal and provides one or more count signals. The clock divider also includes m flip-flops, of which a first flip-flop receives the first input clock signal at its clock input and provides a first clock output signal. Each flip-flop after the first receives an input clock signal at its clock input and provides a clock output signal, each clock output signal after the first having a 2?K/m phase offset from the previous clock output signal.

Abstract: A method of computational lithography includes providing through-focus critical dimension (CD) curves at a range of different focus values (Bossung curves) for a plurality of feature types that include different ratios of line width to space width. Using software run on a computing device, it is determined if there is at least one marginal feature type from the plurality of feature types based an image tool capability and a predetermined process specification affected by at least one of the plurality of feature types. Provided a marginal feature type is determined to be present, at least the marginal feature type(s) is upsized. A degree of upsizing increases as a curvature of the Bossung curves increases. A computational lithography model is compiled including the upsizing.

Abstract: Packets of real-time information are sent with a source rate greater than zero kilobits per second, and a time or path or combined time/path diversity rate initially being zero kilobits per second. This results in a quality of service QoS, optionally measured at the sender or the receiver. When the QoS is on an unacceptable side of a threshold of acceptability, the sender sends diversity packets at an increased rate. Increasing the diversity rate while either reducing or maintaining the overall transmission rate is new. CELP-based multiple-description data partitioning sends the base or important information plus a subset of fixed excitation in one packet and sends the base or important information plus the complementary subset of fixed excitation in another packet. Reconstruction produces acceptable quality when only one of the two packets is received and better quality when both packets are received. Reconstruction provides for single and multiple lost packets.

Abstract: An electronic device and a method for operating an electronic device, wherein the electronic device comprises a reset stage which is configured to have a power down threshold and a power cycle threshold. The voltage level of the power cycle threshold is lower than the voltage level of the power down threshold. The two threshold levels define a first and second interval for a supply voltage of the electronic device. A first interval is between the power cycle threshold and the power down threshold. A second interval is above the power down threshold. The reset stage is further configured to provide the control signal having a defined first state in the first interval and a defined second state in the second interval. The electronic device is set to a low power reset mode if the control signal is in the first state and the electronic device is enabled to enter an active mode if the control signal is in the second state.