Abstract: Functional circuits and cores of circuits are tested on integrated circuits using scan paths. Using parallel scan distributor and collector circuits for these scan paths improves test access of circuits and cores embedded within ICs and reduces the IC's power consumption during scan testing. A controller for the distributor and collector circuits includes a test control register, a test control state machine and a multiplexer. These test circuits can be connected in a hierarchy or in parallel. A conventional test access port or TAP can be modified to work with the disclosed test circuits.

Abstract: A computer device (2010) with a file system having clusters and meta data. The computer device (2010) includes a processor (1030) and a storage (1025) coupled to the processor and having physical representations of instructions so that the processor is operable to reserve (230) at least one of the clusters and to create a log record when meta data for the file system is to be updated by a write (240) of such meta data beforehand to such a reserved cluster, and then set (250) at least one state entry to substantially represent readiness to write the meta data to the file system.

Abstract: An integrated circuit (IC) includes a substrate having a top semiconductor surface including at least one MOS device including a source and a drain region spaced apart to define a channel region. A SiON gate dielectric layer that has a plurality of different N concentration portions is formed on the top semiconductor surface. A gate electrode is on the SiON layer. The plurality of different N concentration portions include (i) a bottom portion extending to the semiconductor interface having an average N concentration of <2 atomic %, (ii) a bulk portion having an average N concentration >10 atomic %, and (iii) a top portion on the bulk portion extending to a gate electrode interface having an average N concentration that is ?2 atomic % less than a peak N concentration of the bulk portion.

Abstract: An electronic assembly includes a workpiece, a through substrate via (TSV) die including a substrate and a plurality of TSVs, a topside and a bottomside having TSV connectors thereon. The TSV die is attached to the workpiece with its topside on the workpiece. A heat spreader having an inner open window is on the bottomside of the TSV die. Bonding features are coupled to the TSV connectors or include the TSV connectors themselves. The bonding features protrude from the inner open window to a height above a height of the top of the heat spreader that allows a top die to be bonded thereto.

Abstract: In at least some embodiments, a system includes a multiple-input multiple-output (MIMO) base station and a plurality of MIMO user equipment (UE) devices in communication with the MIMO base station. The MIMO base station is configured to switch between a single-user (SU)-MIMO mode and a multiple-user (MU)-MIMO mode during communications with the plurality of MIMO UE devices based on multi-rank precoding matrix indicator (PMI) feedback received from at least one of the MIMO UE devices.

Abstract: One aspect of the invention pertains to an integrated circuit package with an embedded power stage. The integrated circuit package includes a first field effect transistor (FET) and a second FET that are electrically coupled with one another. The FETs are embedded in a dielectric substrate that is formed from multiple dielectric layers. The dielectric layers are laminated together with one or more foil layers that help form an electrical interconnect for the package. Various embodiments relate to method of forming the above package.

Abstract: A z-axis fluxgate magnetometer is formed in a semiconductor wafer fabrication sequence, which significantly reduces the size and cost of the fluxgate magnetometer. The semiconductor wafer fabrication sequence forms a vertical magnetic core structure, a first wire structure wound around the magnetic core structure, and a second wire structure wound around the magnetic core structure.

Abstract: An electronic circuit comprises a digital-to-analog converter (DAC) core circuit having a current source device and a digital input bit. An isolation circuit is also provided and is connected to the DAC core circuit. The isolation circuit is configured to selectively provide a source bias signal to the current source device. The isolation circuit also is configured to isolate the source bias signal from the current source device based on a state of the digital input bit.

Abstract: A method of screening static random access memory (SRAM) arrays to identify memory cells with bit line side pass transistor defects. After writing a known data state to the memory cells under test, a forward back-bias is applied to the load transistors of those cells. A write of the opposite data state is then performed, followed by a read of the memory cells. The process is repeated for the opposite data state.

Abstract: The disclosure describes novel methods and apparatuses for controlling a device's TCA circuit when the device exists in a JTAG daisy-chain arrangement with other devices. The methods and apparatuses allow the TCA test pattern set used during device manufacturing to be reused when the device is placed in a JTAG daisy-chain arrangement with other devices, such as in a customers system using the device. Additional embodiments are also provided and described in the disclosure.

Abstract: A pnp SiGe heterojunction bipolar transistor (HBT) reduces the rate that p-type dopant atoms in the p+ emitter of the transistor out diffuse into a lowly-doped region of the base of the transistor by epitaxially growing the emitter to include a single-crystal germanium region and an overlying single-crystal silicon region.

Abstract: A multibit combined multiplexer and flip-flop circuit has a plurality of bit circuits. Each bit circuit includes and input section, a flip-flop section and a per bit control section. The input sections have inputs for plural of input signals and corresponding input pass gates. The outputs of the input pass gates are connected to the input of the flip-flop section. Each per bit control section includes an inverter for each input terminal. There is a combined control section receiving a clock signal and a control signals for selection of only one of the input signals. The combined control section include a logical AND for each input signal combining the clock signal and the selection signal. The output of each logical AND is connected to the input of a corresponding inverter of each per bit control circuit. The input pass gate are controlled by a corresponding logical AND and said corresponding inverter.

Abstract: A successive approximation analog to digital converter (SA-ADC) employs a binary-weighted digital to analog converter (DAC) to perform a non-binary search in determining a digital representation of a sample of an analog signal. In an embodiment, a subset of iterations needed to convert an analog sample to a digital value is performed using non-binary search with a radix of conversion less than two. As a result, search windows in iterations corresponding to the non-binary search overlap, and correction of errors due to a comparator used in the SA-ADC is rendered possible. Error correction being possible due to the non-binary search, the comparator is operated in a low-bandwidth, and hence low-power, mode during the non-binary search. The non-binary search in combination with the binary-weighted architecture of the DAC offer several benefits such as for example, less-complex implementation, shorter conversion time, easier and compact layout and lower power consumption.

Abstract: A GNSS navigation system and navigation method for determining user position, user velocity, and improved uncertainty metrics for position and velocity. A measurement engine in an applications processor of the system determines pseudorange and delta range values over each time period for each received satellite signal, and also determines measurement noise variances for both pseudorange and delta range for the individual signals. The satellite-specific pseudorange and delta range measurement variances are used to determine the position and velocity uncertainties by a position engine, either by way of a least-squares linearization or by way of an enhanced Kalman filter. The uncertainties may be communicated to the system user, or used in generating an integrated position and velocity result from both the GNSS navigation function and an inertial navigation system result.

Abstract: The disclosed invention is a solar tracker that is a simple 2 axis system that can be powered with integrated stepping motors and lead screw actuators that provides the necessary structural support and 2 degrees of freedom in the motion of the solar collector, to increase the electrical output of the system. Since the solution is designed for use with only one solar panel the mechanical forces such as wind load are much lower and easier to manage. The disclosed invention is also a solar tracker that is a single axis version where the base is fixed and the elevation is set at an average value for the location and pivoting mechanism operates the azimuth axis. Since the dominant energy improvement comes from tracking the azimuth, this would be a likely solution where a lower cost or less complex system is desired.

Abstract: An orthotic device comprises a flexible support structure comprising at least one surface for contacting a body part of a user, a plurality of pressure sensors configured for coupling to a microcontroller, and a plurality of displacement regions. Each region defines a portion of said flexible support structure, wherein each portion includes at least one sensor disposed on or below the at least one surface and at least one electrically deformable unit. Each unit comprises at least one electroactive material and is configured for coupling to the microcontroller and to a power source. The device is dynamically adjustable to change its shape and support properties, when an electrical voltage is applied to the electroactive material under the control of a microcontroller.

Abstract: The invention includes a successive approximation register, a digital-to-analog converter, a comparator and a control stage. The control stage initially sets the successive approximation register to a first digital value. The digital-to-analog converter converts the digital value stored in the successive approximation register to an analog value. The comparator compares the converted digital value with an analog input value. The control stage restricts subsequent analog-to-digital conversion for the analog input value to a search interval above or below the first digital value depending on whether the analog input value is greater or lower than the converted analog value of the first digital value.

Abstract: This invention uses multiple codecs to efficiently achieve the right balance between compression and coverage for a given design. This application illustrates a simple example using two codecs including a high compression codec and a low compression codec. The test engineer generates a first set of test patterns using the high compression codec. If this high compression results in unacceptable fault coverage loss, the top-up patterns for additional coverage are generated using the low compression codec. The invention may use multiple codecs serially one after the other. The codecs can be of different types or parameters (such as compression ratio, debug tolerance and combinational codec versus sequential codec).

Abstract: Profiling operating context. At least some of the illustrative embodiments are a computer-readable medium storing a program that, when executed by a processor, causes the processor to obtain values indicative of a state of an operating context parameter during execution of a traced program on a target processor, and display an indication of a proportion of time during a trace period of the traced program that the target processor operated with the operating context parameter in a particular state.

Abstract: A method for filtering a signal having a series of symbols to be transmitted using the default coefficients, detecting occurrence of a series of consecutive common symbols followed by a different symbol in the series of symbols and based on detecting the occurrence, changing from the default coefficients to a second set of coefficients.