Abstract: A circuit includes a bandpass filter and a self-tracking circuit. The bandpass filter has a first input node configured to receive an input square wave signal and an output node configured to provide an output sine wave signal. The bandpass filter includes a first binary-weighted programmable resistor array. The self-tracking circuit includes a second input node coupled to the output node. The self-tracking circuit includes a counter, and the counter includes an output node coupled to the first binary weighted programmable resistor array.

Abstract: A level shifting circuit for a voltage level translator includes first and second cross-coupled level shifters, each coupled between an output supply voltage and a lower rail and further coupled to receive first and second input control signals and to provide an output control signal. The second cross-coupled level shifter includes a first PMOS transistor coupled in series with a first NMOS transistor and a second PMOS transistor coupled in series with a second NMOS transistor. When an input supply voltage is less than a VCCI trigger associated with the output supply voltage, only the first and second NMOS transistors are coupled to contribute to the output control signal and when the input supply voltage is equal to or greater than the VCCI trigger, only the first and second PMOS transistors are coupled to contribute to the output control signal.

Abstract: Systems and methods for fall-back rate-matching and timing for user equipment (UE) configured for downlink (DL) Coordinated Multi-Point Transmission (CoMP) are disclosed. In one embodiment, when a UE configured in DL CoMP receives a fall-back transmission, PDSCH is rate-matched around the serving cell CRS. In an alternative embodiment, when a UE configured in DL CoMP receives a fall-back transmission, PDSCH is rate-matched or uses timing around one of the cell-specific reference symbol (CRS) resource element (RE) set indicated by RRC-higher layer signaling. For example, PDSCH may be rate-matched or use timing around the first RRC higher layer configured CRS RE set.

Abstract: A circuit includes a first filter, a plurality of binary-weighted capacitors, and a current source device. The circuit also includes a first plurality of switches. Each of the first plurality of switches is connected to a separate capacitor of the plurality of binary-weighted capacitors. The first plurality of switches are connected together, and the first plurality of switches are not connected to the first filter. A second plurality of switches is also included, and each of the second plurality of switches is connected to a separate capacitor of the plurality of binary-weighted capacitors and to the first filter and to a control input of the current source device. The first plurality of switches are not connected to the control input.

Abstract: An integrated circuit (IC) includes a substrate having a semiconductor surface layer with functional circuitry for realizing at least one circuit function, with an inter level dielectric (ILD) layer on a metal layer that is above the semiconductor surface layer. A thin film resistor (TFR) including a TFR layer is on the ILD layer. At least one vertical metal wall is on at least two sides of the TFR. The metal walls include at least 2 metal levels coupled by filled vias. The functional circuitry is outside the metal walls.

Abstract: Methods and apparatus for surface wetting control are disclosed. In certain described examples, an apparatus can expel fluid from a droplet on a surface using a transducer mechanically coupled to the surface. A first area of the surface can have a first wettability for the fluid, and a second area of the surface can have a second wettability for the fluid. The first wettability of the first area of the surface can be greater than the second wettability of the second area of the surface. The first area and the second area can be arranged in a patterned arrangement.

Abstract: An energy storage element control circuit includes a charge transistor having a first node adapted to be coupled to an output node of the energy storage element control circuit and a second node adapted to be coupled to a terminal of an energy storage element. The energy storage control circuit also includes a boot capacitor having a first node and a second node. The energy storage element further includes a comparator that includes a first input node coupled to the first node of the charge transistor and a second input node adapted to be coupled to the terminal of the energy storage element. The comparator also includes an output node.

Abstract: A wafer test probe system, probe card, and method to test back-to-back connected first and second transistors of a wafer. The probe card includes a waveform generator circuit and probe needles to couple the waveform generator circuit to provide a first pulse signal of a first polarity using a body diode of the first transistor to test the second transistor, and to provide a second pulse signal of a second polarity using a body diode of the second transistor to the test the first transistor. One example includes a resistor connected between the waveform generator circuit and one of the probe needles. The probe card includes a probe needle to connect a sense transistor of the wafer to the first transistor during wafer probe testing.

Abstract: A second touch area provided on the back side of the mobile phone in a location such that an index finger can be used to provide input when while the mobile phone is being held in that one hand. A second hand is not required for the various types of input that are provided using this second touch area. This allows the mobile phone to be used in single-handed operation in many circumstances.

Abstract: An exhaust gas sensing system includes a channel for flow of exhaust gas, a first directional antenna, a second directional antenna, a first transmitter, a first receiver, and signal processing circuitry. The first directional antenna and the second directional antenna are disposed in the channel. The first transmitter is coupled to the first directional antenna. The first receiver is coupled to the second directional antenna. The signal processing circuitry is coupled to the first transmitter and the first receiver.

Abstract: A hardware thread scheduler (HTS) is provided for a multiprocessor system. The HTS is configured to schedule processing of multiple threads of execution by resolving data dependencies between producer modules and consumer modules for each thread. Pattern adaptors may be provided in the scheduler that allows mixing of multiple data patterns across blocks of data. Transaction aggregators may be provided that allow re-using the same image data by multiple threads of execution while the image date remains in a given data buffer. Bandwidth control may be provided using programmable delays on initiation of thread execution. Failure and hang detection may be provided using multiple watchdog timers.

Abstract: A device includes a pulse generation circuit configured to cause a primary side of a flyback converter to generate a burst of pulses while a signal is enabled, a set-reset latch configured to output the signal and to reset in response to a number of pulses in the burst approaching a threshold, a comparator configured to set the set-reset latch when a compensated feedback voltage reaches a reference voltage, and a ripple compensation circuit configured to adjust a feedback voltage from a secondary side of the flyback converter by a compensation voltage to generate the compensated feedback voltage.

Abstract: A radar system is provided that includes a radar transceiver integrated circuit (IC) configurable to transmit a first frame of chirps, and another radar transceiver IC configurable to transmit a second frame of chirps at a time delay ?T, wherein ?T=Tc/K, K?2 and Tc is an elapsed time from a start of one chirp in the first frame and the second frame and a start of a next chirp in the first frame and the second frame, wherein the radar system is configured to determine a velocity of an object in a field of view of the radar system based on first digital intermediate frequency signals generated responsive to receiving reflected chirps of the first frame and second digital IF signals generated responsive to receiving reflected chirps of the time delayed second frame, wherein the maximum measurable velocity is increased by a factor of K.

Abstract: A primary side wireless power transmitter inductively couplable to a secondary side wireless power receiver for supplying power to the wireless power receiver for receiving communications from the secondary side wireless power receiver through the inductive coupling comprises a primary side tank circuit receiving a signal on from the secondary side wireless power receiver. A phase delay or time delay circuit generates a fixed delay clock signal. A sample and hold circuit samples a tank circuit voltage utilizing the fixed phase or time delayed clock signal. A comparator is coupled to an output of the sample and hold circuit for extracting data or commands from the signal stream. A method of operating a primary side wireless transmitter inductively coupled to a secondary side wireless power receiver for supplying power to the wireless power receiver to power a load coupled to the receiver is also disclosed.

Abstract: An integrated circuit includes a bit slicing circuit with a processing circuit. The processing circuit receives discrete frequency power estimates based on an S-FSK waveform received by an S-FSK receiver associated with the bit slicing circuit. The discrete frequency power estimates are representative of digital logic levels in a series of data frames modulated using S-FSK to form the S-FSK waveform. Each data frame including at least one word. Each word includes bit periods. The processing circuit receives SNR parameters that represent a dynamic SNR for the respective discrete frequency power estimates in relation to the series of data frames. The processing circuit selects a bit slicing technique from a set of available bit slicing techniques to generate data bit values for bit periods of the discrete frequency power estimates based on the SNR parameters. A method for performing bit slicing in an S-FSK receiver is also disclosed.

Abstract: A circuit includes a false circuit path in a circuit under test having a starting logic point to an end logic point of the path. The false circuit path is designated as a testing path to be excluded during testing of one or more valid timing paths of the circuit under test. A false path gating circuit gates the starting logic point to the end logic point of the false circuit path. The false path gating circuit disables the false circuit path in response to one or more gating controls asserted during the testing of the one or more valid timing paths of the circuit under test.

Abstract: Predictive battery pack cell balancing apparatus and methods are presented in which active bypass current switching is controlled according to initial balancing bypass current values to balance the cell depth of discharge (DOD) values by the end of a charging/discharging time period, and according to continuous balancing bypass current values representing an amount of bypass current needed to maintain a present relationship of the cell DOD values.

Abstract: A direct conversion wireless transmitter includes IQ mismatch pre-compensation using direct learning adaptation to adjust IQ pre-compensation filtering. Widely-linear IQ_mismatch pre-compensation filtering compensates for IQ mismatch in the TX analog chain, filtering of input data x(n) to provide pre-compensated data y(n) with a compensation image designed to interfere destructively with the IQ_mismatch image. A feedback receiver FBRX captures feedback data z(n) used for direct learning adaptation. DL adaptation adjusts IQ_mismatch filters, modeled as an x(n)_direct and complex conjugate x(n)_image transfer functions w1 and w2, including generating an adaptation error signal based on a difference between TX/FBRX-path delayed versions of x(n) and z(n), and can include estimation and compensation for TX/FBRX phase errors. DL adaptation adjusts the IQ pre-comp filters w1/w2 to minimize the adaptation error signal. Similar modeling can be used for IQ mismatch.

Abstract: A method for in-loop filtering in a video encoder is provided that includes determining filter parameters for each filtering region of a plurality of filtering regions of a reconstructed picture, applying in-loop filtering to each filtering region according to the filter parameters determined for the filtering region, and signaling the filter parameters for each filtering region in an encoded video bit stream, wherein the filter parameters for each filtering region are signaled after encoded data of a final largest coding unit (LCU) in the filtering region, wherein the in-loop filtering is selected from a group consisting of adaptive loop filtering and sample adaptive offset filtering.

Abstract: A word data loading circuit for a spatial light modulator includes a shadow load register (SLR), a load controller, and a word pattern generation (WPG) circuit. The SLR loads a first word of a pseudorandom image pattern. The load controller parallel shifts the first word to a memory cell array. The WPG circuit generates a next word and controls the SLR to change the first word to the next word. The load controller parallel shifts the next word to the array. The WPG circuit generates an additional word and controls the SLR to change the next word to the additional word. The load controller parallel shifts the additional word to the array. The WPG circuit, SLR, and load controller generate and parallel shift further additional words to the array until the pseudorandom image pattern is loaded in the array.