Patents Assigned to Texas Instruments
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Publication number: 20130227365Abstract: A system comprises a plurality of components, scan chain selection logic coupled to the components, and override selection logic coupled to the scan chain selection logic. The scan chain selection logic selects various of the components to be members of a scan chain under the direction of a host computer. The override selection logic detects a change in the scan chain and, as a result, blocks the entire scan chain from progressing.Type: ApplicationFiled: April 10, 2013Publication date: August 29, 2013Applicant: Texas Instruments IncorporatedInventor: Texas Instruments Incorporated
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Publication number: 20130227377Abstract: An electronic circuit (2250) for a satellite receiver (100, 2200). The electronic circuit (2250) includes a correlator circuit (2310) operable to supply a data signal including ephemeris data and a subsequent satellite time datum, and a data processor (2370, 2380) operable to infer satellite time TS from as few as one of the ephemeris data prior to the satellite time datum. Other circuits, devices, receivers, systems, processes of operation and processes of manufacture are also disclosed.Type: ApplicationFiled: April 11, 2013Publication date: August 29, 2013Applicant: Texas Instruments IncorporatedInventor: Texas Instruments Incorporated
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Publication number: 20130227364Abstract: A device test architecture and interface is provided to enable efficient testing embedded cores within devices. The test architecture interfaces to standard IEEE 1500 core test wrappers and provides high test data bandwidth to the wrappers from an external tester. The test architecture includes compare circuits that allow for comparison of test response data to be performed within the device. The test architecture further includes a memory for storing the results of the test response comparisons. The test architecture includes a programmable test controller to allow for various test control operations by simply inputting an instruction to the programmable test controller from the external tester. The test architecture includes a selector circuit for selecting a core for testing. Additional features and embodiments of the device test architectures are also disclosed.Type: ApplicationFiled: April 8, 2013Publication date: August 29, 2013Applicant: Texas Instruments IncorporatedInventor: Texas Instruments Incorporated
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MOS TRANSISTORS INCLUDING SiON GATE DIELECTRIC WITH ENHANCED NITROGEN CONCENTRATION AT ITS SIDEWALLS
Publication number: 20130221451Abstract: A method of forming an integrated circuit (IC) having at least one MOS device includes forming a SiON gate dielectric layer on a silicon surface. A gate electrode layer is deposited on the SiON gate layer and then patterning forms a gate stack. Exposed gate dielectric sidewalls are revealed by the patterning. A supplemental silicon oxide layer is formed on the exposed SiON sidewalls followed by nitriding. After nitriding, a post nitridation annealing (PNA) forms an annealed N-enhanced SiON gate dielectric layer including N-enhanced SiON sidewalls, wherein along lines of constant thickness a N concentration at the N-enhanced SiON sidewalls is ? the N concentration in a bulk of the annealed N-enhanced SiON gate layer ?2 atomic %. A source and drain region on opposing sides of the gate stack are formed to define a channel region under the gate stack.Type: ApplicationFiled: April 4, 2013Publication date: August 29, 2013Applicant: Texas Instruments IncorporatedInventor: Texas Instruments Incorporated -
Publication number: 20130222069Abstract: Systems and methods of low power clocking of sleep mode radios are disclosed herein. In an example embodiment, a crystal oscillator is purposefully mistuned to achieve lower power consumption, and then synchronized using a high frequency crystal oscillator. In an alternative embodiment, the input offset voltages of the comparator in an RC oscillator are cancelled, which allows low power operation and high accuracy performance when tuned to the high frequency crystal. A lower power comparator may be used with higher input offset voltages but still achieve higher accuracy. The RC circuit is switched back and forth on opposite phases of the output, cancelling the offset voltage on the inputs of the comparator.Type: ApplicationFiled: February 28, 2012Publication date: August 29, 2013Applicant: Texas Instruments IncorporatedInventors: Arun Paidimarri, Danielle Griffith, Alice Wang
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Publication number: 20130227363Abstract: An optimized JTAG interface is used to access JTAG Tap Domains within an integrated circuit. The interface requires fewer pins than the conventional JTAG interface and is thus more applicable than conventional JTAG interfaces on an integrated circuit where the availability of pins is limited. The interface may be used for a variety of serial communication operations such as, but not limited to, serial communication related integrated circuit test, emulation, debug, and/or trace operations.Type: ApplicationFiled: April 3, 2013Publication date: August 29, 2013Applicant: Texas Instruments IncorporatedInventor: Texas Instruments Incorporated
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Publication number: 20130222181Abstract: Enhancing search capacity of Global Navigation Satellite System (GNSS) receivers. A method for searching satellite signals in a receiver includes performing a plurality of searches sequentially. The method also includes storing a result from each search of the plurality of searches in a consecutive section of a memory. Further, the method includes detecting free sections in the memory. The method also includes concatenating the free sections in the memory to yield a concatenated free section. Moreover, the method includes allocating the concatenated free section for performing an additional search.Type: ApplicationFiled: April 10, 2013Publication date: August 29, 2013Applicant: Texas Instruments IncorporatedInventor: Texas Instruments Incorporated
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Publication number: 20130221342Abstract: An apparatus is provided. In the apparatus, there is comprises a substrate with a first region of a first conductivity type, a second region of a second conductivity type that is substantially surrounded by the first region, and a third region of the second conductivity type that is substantially surrounded by the second region. A first dielectric layer is formed over the substrate, and a first conductive layer is formed over the first dielectric layer, which is configured to form a first electrode of a capacitor. A second dielectric layer is formed over the first conductive layer. A plate is formed over the second dielectric layer so as to form a second electrode of the capacitor. A cap is formed over the second dielectric layer, being spaced apart from the plate. A via is electrically coupled to the cap and the third region, extending through the first and second dielectric layers.Type: ApplicationFiled: February 28, 2012Publication date: August 29, 2013Applicant: Texas Instruments IncorporatedInventors: Kannan Soundarapandian, Benjamin Amey, Timothy Paul Duryea
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Patent number: 8522093Abstract: Topology discovery of a target system having a plurality of components coupled with a scan topology may be performed by driving a low logic value on the data input signal and a data output signal of the scan topology. An input data value and an output data value for each of the plurality of components is sampled and recorded. A low logic value is then scanned through the scan path and recorded at each component. The scan topology may be determined based on the recorded data values and the recorded scan values.Type: GrantFiled: July 27, 2012Date of Patent: August 27, 2013Assignee: Texas Instruments IncorporatedInventor: Gary L. Swoboda
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Patent number: 8519753Abstract: Here, an apparatus is provided. The apparatus comprises a first supply rail, a second supply rail, a first ambipolar transistor (which is coupled to the first supply rail at its drain and which receives a reference voltage at its gate), a second ambipolar transistor (which is coupled to the first supply rail at its drain and which receives an input signal at its gate), a current source (which is coupled between the sources of the first and second ambipolar transistors and the second supply rail), and an output circuit (which is coupled to drain of the first ambipolar transistor). In operation, the output circuit provides an output signal having a frequency that is about twice the frequency of the input signal.Type: GrantFiled: December 13, 2010Date of Patent: August 27, 2013Assignee: Texas Instruments IncorporatedInventor: Andrew Marshall
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Patent number: 8522094Abstract: Connection circuitry couples scan test port (STP) circuitry to test access port (TAP) circuitry. The connection circuitry has inputs connected to scan circuitry control output leads from the TAP circuitry, a select input lead, and a clock input lead. The connection circuitry has outputs connected to a scan enable (SE) input lead, a capture select (CS) input lead, and the scan clock (CK) input lead of the STP circuitry. The connection circuitry includes a multiplexer having a control input connected with a clock select lead from the TAP circuitry, an input connected with a functional clock lead, an input connected with the clock input lead, an input connected with a Clock-DR lead from the TAP circuitry, an OFF lead, and an output connected with the scan clock input lead.Type: GrantFiled: November 15, 2012Date of Patent: August 27, 2013Assignee: Texas Instruments IncorporatedInventor: Lee D. Whetsel
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Patent number: 8519773Abstract: A method for switching between first and second voltages is provided. Initially, a first voltage is provided from a first input terminal to an output terminal through a first MOS transistor, and the first MOS transistor is deactivated. A back-gate of a second MOS transistor is shorted to the output terminal in response to the deactivation of the first MOS transistor and after a settling interval, and the second MOS transistor is activated while its back-gate is shorted to the terminal so as to provide a second voltage from a second input terminal to the output terminal.Type: GrantFiled: June 17, 2011Date of Patent: August 27, 2013Assignee: Texas Instruments IncorporatedInventors: Hiroshi Watanabe, Hiroaki Kojima, Kazuya Machida
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Patent number: 8522095Abstract: The disclosure provides a novel method and apparatus for inputting addresses to devices to select the device TAP for access. Further, the disclosure provides a novel method and apparatus for inputting addresses for selecting device TAPs and for inputting commands for commanding circuitry within the device. The inputting of addresses or the inputting of addresses and commands is initiated by a control bit input on TDI that is recognized during the Run Test/Idle, Pause-DR or Pause-IR TAP states.Type: GrantFiled: September 13, 2012Date of Patent: August 27, 2013Assignee: Texas Instruments IncorporatedInventor: Lee D. Whetsel
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Patent number: 8519791Abstract: A method is provided. A first enable signal is asserted so as to enable a first driver, where the first driver has a first output and a first parasitic capacitance. A second enable signal is asserted so as to enable a second driver, where the second driver has a second output and a second parasitic capacitance. The first and second outputs are coupled together by a switching network when the second driver is enabled. Pulses from complementary first and second radio frequency (RF) signals are applied to the first driver, where there is a first set of free-fly intervals between consecutive pulses from the first and second RF signals, and pulses from complementary third and fourth RF signals are applied to the second driver, wherein there is a second set of free-fly interval between consecutive pulses from the third and fourth RF signals.Type: GrantFiled: March 9, 2012Date of Patent: August 27, 2013Assignee: Texas Instruments IncorporatedInventors: Joonhoi Hur, Lei Ding, Rahmi Hezar, Baher S. Haroun
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Patent number: 8522092Abstract: A scan test architecture facilitates low power testing of semiconductor circuits by selectively dividing the serial scan paths into shorter sections. Multiplexers between the sections control connecting the sections into longer or shorted paths. Select and enable signals control the operation of the scan path sections. The output of each scan path passes through a multiplexer to compare circuits on the semiconductor substrate. The compare circuits also receive expected data and mask data. The compare circuits provide a fail flag output from the semiconductor substrate.Type: GrantFiled: April 30, 2012Date of Patent: August 27, 2013Assignee: Texas Instruments IncorporatedInventor: Lee D. Whetsel
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Patent number: 8522098Abstract: The disclosure describes a novel method and apparatus for providing expected data, mask data, and control signals to scan test architectures within a device using the falling edge of a test/scan clock. The signals are provided on device leads that are also used to provide signals to scan test architectures using the rising edge of the test/scan clock. According to the disclosure, device test leads serve to input different test signals on the rising and falling edge of the test/scan clock which reduces the number of interconnects between a tester and the device under test.Type: GrantFiled: June 1, 2012Date of Patent: August 27, 2013Assignee: Texas Instruments IncorporatedInventor: Lee D. Whetsel
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Patent number: 8519873Abstract: In higher order sigma-delta modulators (SDMs), there are oftentimes errors introduced by the digital-to-analog (DAC) switches. Namely, parasitic capacitances associated with switches can introduce second harmonic spurs. Here, however, compensation circuits and buffers are provided. The buffers bias the switches in saturation, and the compensation circuits provide a “ground boost” for the buffers. The combination of the buffer and compensation circuit reduces the second harmonic spur, while also improving the Signal-to-Noise Ratio (SNR) and Signal-to-Noise-plus-Distortion Ratio (SNDR).Type: GrantFiled: September 9, 2011Date of Patent: August 27, 2013Assignee: Texas Instruments IncorporatedInventors: Venkatesh Srinivasan, Vijay B. Rentala, Victoria W. Limetkai, Baher Haroun
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Patent number: 8519877Abstract: A circuit for providing audio signals to a load such as a speaker is provided that uses the speaker or headphone amplifier structure as a current to voltage converter, thereby eliminating a separate current to voltage converter from the circuit. Such a design removes one of the elements that creates noise in the circuit architecture and improves the dynamic range for the audio signal. For example, the output of a digital to analog converter is a single ended output provided to the speaker or headphone amplifier. The digital to analog converter can include a series of current sources that are summed up to provide the single ended output. Where the current sources have positive and negative current source mismatch, a feedback mechanism is employed to correct for the mismatch and reduce introduction of harmonic noise into the signal through the digital to analog converter.Type: GrantFiled: March 28, 2012Date of Patent: August 27, 2013Assignee: Texas Instruments IncorporatedInventor: Shailendra Kumar Baranwal
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Publication number: 20130217216Abstract: One embodiment of the invention relates to an unguarded Schottky barrier diode. The diode includes a cathode that has a recessed region and a dielectric interface surface that laterally extends around a perimeter of the recessed region. The diode further includes an anode that conforms to the recessed region. A dielectric layer extends over the dielectric interface surface of the cathode and further extends over a portion of the anode near the perimeter. Other devices and methods are also disclosed.Type: ApplicationFiled: April 5, 2013Publication date: August 22, 2013Applicant: Texas Instruments IncorporatedInventor: Texas Instruments Incorporated
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Publication number: 20130214159Abstract: In conventional membrane infrared (IR) sensors, little to no attention has been paid toward transmissivity of IR near metal traces. Here, because the substrate of an integrated circuit carrying the sensor is used as a visible light filter, reflection of IR radiation back into the substrate can affect the operation and reliability of the IR sensor. As a result, an arrangement is provided that reduces the area occupied by metal lines by reducing the pitch and compacting the routing so as to reduce the effects from the reflection of IR radiation by metal traces.Type: ApplicationFiled: April 3, 2013Publication date: August 22, 2013Applicant: Texas Instruments IncorporatedInventor: Texas Instruments Incorporated
