Abstract: An integrated circuit containing a first plurality of MOS transistors operating in a low voltage range, and a second plurality of MOS transistors operating in a mid voltage range, may also include a high-voltage MOS transistor which operates in a third voltage range significantly higher than the low and mid voltage ranges, for example 20 to 30 volts. The high-voltage MOS transistor has a closed loop configuration, in which a drain region is surrounded by a gate, which is in turn surrounded by a source region, so that the gate does not overlap field oxide. The integrated circuit may include an n-channel version of the high-voltage MOS transistor and/or a p-channel version of the high-voltage MOS transistor. Implanted regions of the n-channel version and the p-channel version are formed concurrently with implanted regions in the first and second pluralities of MOS transistors.

Abstract: An open drain driver circuit includes an output terminal, an input terminal, a first transistor, a second transistor, and a third transistor. The first transistor includes a first terminal coupled to the output terminal, and a second terminal coupled to a reference voltage source. The second transistor includes a first terminal coupled to a third terminal of the first transistor, a second terminal coupled to a power supply rail, and a third terminal coupled to the reference voltage source. The third transistor includes a first terminal coupled to the input terminal, a second terminal coupled to the reference voltage source, and a third terminal coupled to the third terminal of the first transistor.

Abstract: A layout file for an integrated circuit has drawn geometries. Variable fill geometries are added to local areas based on densities of the drawn geometries in windows associated with the local areas and on the global density of all the drawn geometries in the layout file. Each window has a separate local area associated with it. The densities of the variable fill geometries in the local areas are not all equal. Densities of the fill geometries are higher in local areas associated with windows having lower densities of the drawn geometries, and for lower values of the global density. The layout file is stored in a computer-readable medium which may be used to produce a photomask for manufacturing an integrated circuit.

Abstract: A semiconductor package includes a leadframe comprising input/output pins accessible external to the semiconductor package and a semiconductor die electrically connected to the leadframe. The semiconductor package also includes a passive electrical component mounted on a side of the semiconductor die opposite the leadframe. Mold compound encapsulates the passive electrical component, semiconductor die, and leadframe to form the semiconductor package. Associated methods are disclosed as well.

Abstract: A device includes a frequency multiplier circuit to receive a base frequency signal, multiply the base frequency signal, and output the multiple of the base frequency signal, and includes an offset frequency generator, including at least one logic gate, to receive the multiple of the base frequency signal and output an offset frequency signal from the at least one logic gate combination. A mixing circuit receives the offset frequency signal and a digital data signal, converts the digital data signal into an analog representation of the digital data signal, and mixes the offset frequency signal and the analog representation of the digital data signal to produce a mixed signal. The device yet further includes a power amplifier to amplify the mixed signal and output the amplified mixed signal as an output frequency signal of the device.

Abstract: A LIDAR system includes a static monolithic LIDAR transceiver, a collimating optic, and a first rotatable wedge prism. The static monolithic LIDAR transceiver is configured to transmit a laser beam and receive reflected laser light from a first target object. The collimating optic is configured to narrow the transmitted laser beam to produce a collimated laser beam. The first rotatable wedge prism is configured to steer the collimated laser beam in a direction of the first target object based on the first rotatable wedge prism being in a first position.

Abstract: A comparator circuit includes a first transistor, a second transistor, a first switch, a second switch, and a timing circuit. The first transistor and the second transistor are coupled as a differential pair and are configured to compare an input signal to a hysteresis voltage. The first switch is coupled to the first transistor and is configured to selectably enable the first transistor. The second switch is coupled to the second transistor and is configured to selectably enable the second transistor. The timing circuit is coupled to the first switch and the second switch and is configured to close the first switch responsive to a signal transition at an output of the comparator circuit and close the second switch a predetermined delay time after the first switch is closed.

Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements. A steam head register stores data elements next to be supplied to functional units for use as operands. The streaming engine stores an early address of next to be fetched data elements and a late address of a data element in the stream head register for each of the nested loops. The streaming engine stores an early loop counts of next to be fetched data elements and a late loop counts of a data element in the stream head register for each of the nested loops.

Abstract: An IQ mismatch correction function generator configured to generate an enhanced IQ mismatch correction function to improve the compensation for IQ mismatch, and an IQ signal receiver with the IQ mismatch correction function generator, wherein the enhanced IQ mismatch correction function is determined based on an initial IQ mismatch correction function derived from IQ mismatch estimates corresponding to frequency bins where signals are present and error of the initial IQ mismatch correction function by comparing the values of the initial IQ mismatch correction function with IQ mismatch estimates corresponding to a respective bin of the frequency bins.

Abstract: A system and method for bonding an electrically conductive mechanical interconnector (e.g., a bonding wire, solder, etc.) to an electrical contact (e.g., contact pad, termination on a printed circuit board (PCB), etc.) made from an electrically conductive metal (e.g., aluminum) on an electronic device (e.g., integrated circuit (IC), die, wafer, PCB, etc.) is provided. The electrical contact is chemically coated with a metal (e.g., cobalt) that provides a protective barrier between the mechanical interconnector and the electrical contact. The protective barrier provides a diffusion barrier to inhibit galvanic corrosion (i.e. ion diffusion) between the mechanical interconnector and the electrical contact.

Abstract: A semiconductor die. The die comprises a level shifter coupled to a positive differential input and to a negative differential input comprising a first operational amplifier, wherein the first operational amplifier is configured to generate an internal common mode voltage coupled to a positive differential output and to a negative differential output, a positive alternating current (AC) coupled feed-forward path comprising a first capacitor coupled to the positive differential input and to the positive differential output, a negative AC coupled feed-forward path comprising a second capacitor coupled to the negative differential input and to the negative differential output, a positive direct current (DC) feed-forward path coupled to the differential input, to the internal common mode voltage sense node, and to the positive differential output, and a negative DC feed-forward path coupled to the differential input, to the internal common mode voltage sense node, and to the negative differential output.

Abstract: A queuing requester for access to a memory system is provided. Transaction requests are received from two or more requestors for access to the memory system. Each transaction request includes an associated priority value. A request queue of the received transaction requests is formed in the queuing requester. Each transaction request includes an associated priority value. A highest priority value of all pending transaction requests within the request queue is determined. An elevated priority value is selected when the highest priority value is higher than the priority value of an oldest transaction request in the request queue; otherwise the priority value of the oldest transaction request is selected. The oldest transaction request in the request queue with the selected priority value is then provided to the memory system. An arbitration contest with other requesters for access to the memory system is performed using the selected priority value.

Abstract: A device (such as for mobile communications) including a capacitive touch-on-surface (ToS) display adapted for capacitive touch-force sensing. A ToS capacitive sensor includes a profiled capacitive sensor electrode, intermediate and spaced from parallel ground plates by elastomeric insulator/dielectric spacer elements. The profiled capacitive sensor electrode has a non-uniform density profile that is relatively lower near a center of the electrode, and relatively higher near edges of the electrode, for example, equalizing touch-force sensitivity such that sensitivity to a touch-force deflection is substantially uniform across the profiled capacitive electrode.

Abstract: A method to fabricate a transistor includes implanting dopants into a semiconductor to form a drift layer having majority carriers of a first type; etching a trench into the semiconductor; thermally growing an oxide liner into and on the trench and the drift layer; depositing an oxide onto the oxide liner on the trench to form a shallow trench isolation region; implanting dopants into the semiconductor to form a drain region in contact with the drift layer and having majority carriers of the first type; implanting dopants into the semiconductor to form a body region having majority carriers of a second type; forming a gate oxide over a portion of the drift layer and the body region; forming a gate over the gate oxide; and implanting dopants into the body region to form a source region having majority carriers of the first type.

Abstract: IEEE 1149.1 Test Access Ports (TAPs) may be utilized at both IC and intellectual property core design levels. TAPs serve as serial communication ports for accessing a variety of embedded circuitry within ICs and cores including; IEEE 1149.1 boundary scan circuitry, built in test circuitry, internal scan circuitry, IEEE 1149.4 mixed signal test circuitry, IEEE P5001 in-circuit emulation circuitry, and IEEE P1532 in-system programming circuitry. Selectable access to TAPs within ICs is desirable since in many instances being able to access only the desired TAP(s) leads to improvements in the way testing, emulation, and programming may be performed within an IC. A TAP linking module is described that allows TAPs embedded within an IC to be selectively accessed using 1149.1 instruction scan operations.

Abstract: A microelectronic device includes a metal layer on a first dielectric layer. An etch stop layer is disposed over the metal layer and on the dielectric layer directly adjacent to the metal layer. The etch stop layer includes a metal oxide, and is less than 10 nanometers thick. A second dielectric layer is disposed over the etch stop layer. The second dielectric layer is removed from an etched region which extends down to the etch stop layer. The etched region extends at least partially over the metal layer. In one version of the microelectronic device, the etch stop layer may extend over the metal layer in the etched region. In another version, the etch stop layer may be removed in the etched region. The microelectronic device is formed by etching the second dielectric layer using a plasma etch process, stopping on the etch stop layer.

Abstract: In described examples, a method for electroplating a semiconductor device includes: forming a metal foil; forming an inert anode support; attaching the metal foil to the inert anode support to form an anode; forming a cathode using a semiconductor substrate; immersing the anode and the cathode within an electrolyte solution; forming a circuit with a current source, the anode and the cathode; generating a current through the circuit; and electroplating a metal from the electrolyte solution onto the semiconductor substrate.

Abstract: An integrated circuit (IC) includes a first capacitor, a second capacitor, and functional circuitry configured together with the capacitors for realizing at least one circuit function in a semiconductor surface layer on a substrate. The capacitors include a top plate over a LOCal Oxidation of Silicon (LOCOS) oxide, wherein a thickness of the LOCOS oxide for the second capacitor is thicker than a thickness of the LOCOS oxide for the first capacitor. There is a contact for the top plate and a contact for a bottom plate for the first and second capacitors.

Abstract: A method for adaptive loop filtering of a reconstructed picture in a video encoder is provided that includes determining whether or not sample adaptive offset (SAO) filtering is applied to the reconstructed picture, and using adaptive loop filtering with no offset for the reconstructed picture when the SAO filtering is determined to be applied to the reconstructed picture.

Abstract: A Convolutional Neural Network (CNN) based-signal processing includes receiving of an encrypted output from a first layer of a multi-layer CNN data. The received encrypted output is subsequently decrypted to form a decrypted input to a second layer of the multi-layer CNN data. A convolution of the decrypted input with a corresponding decrypted weight may generate a second layer output, which may be encrypted and used as an encrypted input to a third layer of the multi-layer CNN data.