Abstract: A phase-locked loop (PLL) including a multiplexer with multiple inputs, each input coupled to receive a different reference clock. A time-to-digital converter (TDC) generates a TDC output value based on a phase difference between a reference clock from the multiplexer and a feedback clock. An averager circuit coupled to an output of the TDC. An adder circuit is coupled to outputs of the TDC and the averager circuit. A loop filter is coupled to an output of the adder circuit.

Abstract: A method and system for bit rate control during encoding of multimedia data are disclosed. A change in complexity of a multimedia picture relative to complexity associated with one or more multimedia pictures in a multimedia sequence is determined. A complexity associated with a multimedia picture is determined based on number of bits and an average quantization associated with the multimedia picture. A bit rate is adjusted for encoding the multimedia picture based on the change in complexity of the multimedia picture. The bit rate is increased on determining an increase in complexity of the multimedia picture and is decreased on determining a decrease in complexity of the multimedia picture. Utilization of additional bits during the increase in the bit rate and saving of bits during the decrease in the bit rate are compensated during adjusting of bit rates for encoding subsequent multimedia pictures in the multimedia sequence.

Abstract: A method of estimating position of an obstacle of a plurality of obstacles with a radar apparatus. An azimuth frequency, an elevation frequency and a range of the obstacle are estimated to generate an estimated azimuth frequency, an estimated elevation frequency and an estimated range of the obstacle. A metric is estimated from one or more of the estimated azimuth frequency, the estimated elevation frequency and the estimated range of the obstacle. The metric is compared to a threshold to detect an error in at least one of the estimated azimuth frequency and the estimated elevation frequency. On error detection, a sign of at least one of the estimated azimuth frequency and the estimated elevation frequency is inverted to generate a true estimated azimuth frequency and a true estimated elevation frequency respectively.

Abstract: Methods and apparatus for performing a high speed phase demodulation scheme using a low bandwidth phase-lock loop are disclosed. An example apparatus includes a low bandwidth phase lock loop to lock to a data signal at a first phase, the data signal capable of oscillating at the first phase or a second phase; and output a first output signal at the first phase and a second output signal at the second phase, the first output signal or the second output signal being utilized in a feedback loop of the low bandwidth phase lock loop. The example apparatus further includes a fast phase change detection circuit coupled to the low bandwidth phase lock loop to determine whether the data signal is oscillating at the first phase or the second phase.

Abstract: A circuit includes a digital-to-analog converter (DAC) having a DAC input and a DAC output. The circuit includes a reference voltage (VREF) generator having a VREF generator input, a VREF generator output, and a VREF power supply input. The VREF generator output is coupled to the DAC input. A voltage regulator has a voltage regulator input and a voltage regulator output. The voltage regulator output is coupled to the DAC. A clamp circuit has a first clamp circuit input, a second clamp circuit input, and a clamp circuit output. The first clamp circuit input is coupled to the voltage regulator input, and the clamp circuit output is coupled to the VREF power supply input. The second clamp circuit input is coupled to the voltage regulator output. The clamp circuit includes a source-follower circuit having the second clamp circuit input.

Abstract: A circuit includes a first signal swapper including a first terminal coupled to a first current source, a second terminal coupled to a second current source, a third terminal coupled to a first current terminal of a first transistor, and a fourth terminal coupled to a third current terminal of a second transistor. The first signal swapper couples the first and second terminals to the third and fourth terminals responsive to a first control signal. First and second switches couple to a gate of the first transistor. The first switch receives the input oscillation signal and the second switch receives a first reference voltage. Third and fourth switches couple to a gate of the second transistor. The third switch receives the input oscillation signal and the fourth switch receives the first reference voltage. A second signal swapper couples to the first signal swapper and to the first and second transistors.

Abstract: A switching circuit includes back-to-back NMOS transistors coupled between first and second pins. A first PMOS transistor is coupled between an upper supply voltage and a first node and has a gate coupled to receive a first enable signal. First and second current mirrors are coupled in series to the first node and a resistor is coupled in parallel with the first current mirror. A first leg of the first and second current mirrors is coupled to a lower supply voltage through a second PMOS transistor and a second leg is coupled to the gates of the back-to-back NMOS transistors. The gate of the second PMOS transistor is coupled to a node that lies between the back-to-back NMOS transistors. Additional NMOS transistors couple the lower supply voltage to the gates and sources of the back-to-back NMOS transistors and also to the gate of the first current mirror.

Abstract: A floating input detection method and circuits. A method for detecting a floating signal input terminal includes providing a common-mode input voltage to a first amplifier coupled to the signal input terminal, and providing an output signal generated by the first amplifier to: a non-inverting input of a second amplifier coupled to the signal input terminal, an inverting input of the second amplifier, coarse detection circuitry, and fine float detection circuitry. The method also includes comparing, by the coarse detection circuitry, the output signal to a first threshold voltage, and determining the signal input terminal to be not floating responsive to the comparing indicating that the output signal is greater than the first threshold voltage.

Abstract: Electronic device manufacturing and configuration methods include performing an additive deposition process that deposits a conductive, resistive, magnetic, semiconductor and/or thermally conductive material over a surface of a processed wafer metallization structure to set or adjust a circuit of a capacitor, an inductor, a resistor, an antenna and/or a thermal component of the metallization structure.

Abstract: A capacitor-drop power supply includes a rectifier and a rectifier controller. The rectifier is configured to receive an alternating current (AC) signal at an AC voltage and convert the AC signal into a rectified direct current (DC) signal at a rectified voltage. The rectifier includes a first low side switch. The rectifier controller is configured to generate a switch close signal based on the rectified DC signal. The switch close signal is configured to close the first low side switch shunting the AC signal to ground.

Abstract: An electronic device, a lead frame, and a method, including providing a lead frame with a Y-shaped feature having branch portions connected to a dam bar in a prospective gap in an equally spaced repeating lead pitch pattern, and a set of first leads extending parallel to one another along a first direction and spaced apart from one another along a second direction in lead locations of the repeating lead pitch pattern, attaching a semiconductor die to a die attach pad of the lead frame, attaching bond wires between bond pads of the semiconductor die, and the first leads, enclosing first portions of the first leads, the die attach pad, and a portion of the semiconductor die in a package structure, and performing a dam bar cut process that cuts through portions of the dam bar between the lead locations of the repeating lead pitch pattern.

Abstract: A packaged electronic device includes a multilayer substrate, including a first side, a first layer having a first plurality of conductive structures along the first side, and a second layer having a second plurality of conductive structures, a semiconductor die soldered to a first set of the conductive structures, a conductive clip directly connected to one of the conductive structures of the first layer and to a second side of the semiconductor die, and a package structure that encloses the semiconductor die and a portion of the conductive clip.

Abstract: An electronic device includes a semiconductor die, an enclosure, leads extending outwardly from the enclosure and electrically connected to the semiconductor die, and wherein the leads have a reduced cross-sectional area along a longitudinal length of the lead. The electronic device is designed to reduce the occurrence of crack formation between the leads and a printed circuit board.

Abstract: Apparatus, systems, and methods disclosed herein operate to provide wireless communication between personal mobile communication (PMC) devices. An emulated wireless access point (AP) at a first PMC device (PMC1) establishes a first tunneled direct link setup (TDLS) session between a first station module (STA1) incorporated into the PMC1 and a second station module (STA2) incorporated into a second PMC device (PMC2). Following establishment of the TDLS session, the wireless AP is allowed to sleep; and most infrastructure management duties are handled by the STA1 during the session. PMC device battery charge may be conserved as a result. The emulated wireless AP may also establish a second TDLS link to a third station module (STA3) incorporated into a third PMC device (PMC3). The STA1 may then bridge data traffic flow between the STA2 and the STA3. Such bridging operation may enable communication between two PMC devices otherwise unable to decode data received from the other.

Abstract: An apparatus is provided. A substrate and a cover plate are provided. A sensor layer is formed on at least one of the substrate and the cover plate. The sensor layer includes a plurality of row electrodes and a plurality of column electrodes interleaved with the plurality of row electrodes, where each row electrode and each column electrode is formed of a plurality of stair-stepped diamonds. An insulator is also included so as to electrically isolate the plurality of row electrodes and the plurality of column electrodes, where the insulator is substantially transparent to visible spectrum light. The apparatus employs mirror symmetric row sensor routing placement. The routing placement provides reduction of row bonding pads by 50% to enhance manufacturing yield. Rearranging unit cells on the same layout results in a decrease of RC parasitics by 50%.

Abstract: A semiconductor system (900) has a flat interposer (510) with a first surface (401a) in a first plane, a second surface (401b) in a parallel second plane, and a uniform first height (401) between the surfaces; the interposer is patterned in metallic zones separated by gaps (412, 415), the zones include metal of the first height and metal of a second height (402) smaller than the first height; an insulating material fills the gaps and the zone differences between the first and the second heights. Semiconductor chips of a first (610) and a second (611) set have first terminals attached to metallic zones of the first interposer surface while the chips of the second set have their second terminals facing away from the interposer. A first leadframe (700) is attached to the second terminals of the second set chips, and a second leadframe (800) is attached to respective metallic zones of the second interposer surface.

Abstract: A circuit includes an operational amplifier and a resistor network coupled to an output of the operational amplifier. The resistor network includes a first set of resistors coupled between the output of the operational amplifier and a first node of the resistor network, wherein the resistors of the first set are electrically connected in series with each other, a second set of resistors coupled between the first node and a second node of the resistor network, wherein the resistors of the second set are electrically connected in series with each other and include a first number of resistors, a third set of resistors coupled between the second node and a third node of the resistor network, wherein the third node is coupled to a first voltage, and wherein the resistors of the third set are electrically connected in parallel with each other and include a second number of resistors, and a resistor coupled between the first node and the second node and arranged in parallel with the second set of resistors.

Abstract: A method for processing a semiconductor wafer in a PECVD deposition chamber with a circular pedestal and a recessed portion formed around the outer top surface of the pedestal. The method may include using a circular wafer carrier ring with a recessed portion.

Abstract: An integrated microfabricated vapor cell sensor includes a transparent sensor cell body. The cell body has a cavity for a sensor fluid vapor which is covered by a first plate attached to the cell body. The sensor has a first signal path extending from a first signal emitter, through the cell body, through the cavity, through the cell body again, and to a first signal detector, and a second signal path extending through the cavity. The second signal path intersects the first signal path in the cavity. The second signal path may extend through the cell body, or may extend through the first plate. The signal emitters and signal detectors are located in the integrated microfabricated vapor cell sensor.

Abstract: A trench capacitor includes at least one epitaxial semiconductor surface layer on a semiconductor substrate having a doping level that is less than a doping level of the semiconductor substrate. A plurality of trenches are formed through at least one half of a thickness of the epitaxial semiconductor surface layer. The epitaxial semiconductor surface layer is thicker than a depth of the plurality of trenches. At least one capacitor dielectric layer lines a surface of the trenches. At least one trench fill layer on the dielectric layer fills the trenches.