Abstract: A trench capacitor includes at least one epitaxial semiconductor surface layer on a semiconductor substrate having a doping level that is less than a doping level of the semiconductor substrate. A plurality of trenches are formed through at least one half of a thickness of the epitaxial semiconductor surface layer. The epitaxial semiconductor surface layer is thicker than a depth of the plurality of trenches. At least one capacitor dielectric layer lines a surface of the trenches. At least one trench fill layer on the dielectric layer fills the trenches.

Abstract: An integrated circuit (IC) is provided with a plurality of diode based mm-wave peak voltage detectors (PVD)s. During a testing phase, a multi-point low frequency calibration test is performed on one or more of the PVDs to determine and store a set of alternating current (AC) coefficients. During operation of the IC, a current-voltage sweep is performed on a selected one of the PVDs to determine a process and temperature direct current (DC) coefficient. A peak voltage produced by the PVD in response to a high frequency radio frequency (RF) signal is measured to produce a first measured voltage. An approximate power of the RF signal is calculated by adjusting the first measured voltage using the DC coefficient and the AC coefficient.

Abstract: An integrated circuit includes a fluxgate magnetometer. The magnetic core of the fluxgate magnetometer is encapsulated with a layer of encapsulant of a nonmagnetic metal or a nonmagnetic alloy. The layer of encapsulate provides stress relaxation between the magnetic core material and the surrounding dielectric. A method for forming an integrated circuit has the magnetic core of a fluxgate magnetometer encapsulated with a layer of a nonmagnetic metal or nonmagnetic alloy to eliminate delamination and to substantially reduce cracking of the dielectric that surrounds the magnetic core.

Abstract: A reference generator provides a reference output voltage that is continuously available while providing certain efficiencies of a duty-cycled voltage regulator. The reference output voltage is generated by a sample-and-hold circuit that is coupled to a voltage regulator. On command, the sample-and-hold circuit samples a low dropout voltage regulator that may be referenced by a bandgap circuit. During hold periods of the sample-and-hold circuit, the voltage regulator, in particular the bandgap circuit, may be disabled in order to conserve power. A sample cycle by the sample-and-hold circuit may be triggered by a signal received from a configurable finite state machine. The reference generator is effectively duty cycled in a manner that conserves available battery power, while still providing a constant reference output that is always available. The reference generator is especially suited for low-power, battery operated applications.

Abstract: A semiconductor device includes a substrate including a semiconductor surface layer. A field plate (FP) includes a trench in the semiconductor surface layer filled with a single polysilicon layer positioned on at least one side of a power metal-oxide-semiconductor field effect transistor (power MOSFET). The power MOSFET includes a dielectric liner lining a sidewall of the trench under the polysilicon layer including a second dielectric liner on a first dielectric liner. An upper portion of the dielectric liner has a lower dielectric thickness as compared to a dielectric thickness on its lower portion. The single polysilicon layer extends continuously over the dielectric liner along both the lower portion and the upper portion. The power MOSFET includes a drain including a drain contact below a vertical drift region in the semiconductor surface layer, and a gate, body and a source above the vertical drift region.

Abstract: Motion compensation requires a significant amount of memory bandwidth, especially for smaller prediction unit sizes. The worst case bandwidth requirements can occur when bi-predicted 4×8 or 8×4 PUs are used. To reduce the memory bandwidth requirements for such smaller PUs, methods are provided for restricting inter-coded PUs of small block sizes to be coded only in a uni-predictive mode, i.e., forward prediction or backward prediction. More specifically, PUs of specified restricted sizes in bi-predicted slices (B slices) are forced to be uni-predicted.

Abstract: Disclosed examples include a segmented DAC circuit, including an R-2R resistor DAC to convert a first subword to a first analog output signal, an interpolation DAC to offset the first analog output signal based on an N-bit digital interpolation code signal to provide the analog output signal, and a Sigma Delta modulator to modulate a modulator code to provide the N-bit digital interpolation code signal that represents a value of second and third subwords.

Abstract: In a powerline communications (PLC) network having a first node and at least a second node on a PLC channel utilizing a band including a plurality of tones, based on at least one channel quality indicator (CQI), the first node allocates for a tone map response payload only a single (1) power control bit for each of a plurality of subbands having two or more tones. The power control bit indicates a first power state or a second power state. The first node transmits a frame including the tone map response payload to the second node. The second node transmits a frame having boosted signal power for the tones in the subbands which have the first power state compared to a lower signal power for the tones in the subbands which have the second power state.

Abstract: Disclosed examples include a resistor comprising a semiconductor structure having a length dimension with first and second ends spaced from one another and an intermediate region between the first and second ends, first and second metal-semiconductor compound structures on the semiconductor structure proximate the first and second ends of the semiconductor structure, the first and second metal-semiconductor compound structures being spaced apart from each other along the length dimension of the semiconductor structure, and at least one intermediate metal-semiconductor compound structure on a portion of the intermediate region of the semiconductor structure between the first and second ends, the intermediate metal-semiconductor compound structure being spaced apart from the first and second metal-semiconductor compound structures on the semiconductor structure.

Abstract: A radio frequency transmitter includes a digital-to-analog converter (DAC), a load circuit, and a modulator circuit. The load circuit is coupled to an output of the DAC. The modulator circuit is coupled to the DAC and the load circuit. The modulator circuit includes a driver circuit configured to provide a bias voltage to the load circuit, and an amplifier configured to receive an output of the DAC biased by an output of the load circuit.

Abstract: A packaged semiconductor device includes a metal substrate having a center aperture with a plurality of raised traces around the center aperture including a metal layer on a dielectric base layer. A semiconductor die that has a back side metal (BSM) layer is mounted top side up in a top portion of the center aperture. A single metal layer directly between the BSM layer and walls of the metal substrate bounding the center aperture to provide a die attachment that fills a bottom portion of the center aperture. Leads having at least one bend that contact the metal layer are on the plurality of traces and include a distal portion that extends beyond the metal substrate. Bond wires are between the traces and bond pads on the semiconductor die. A mold compound provides encapsulation.

Abstract: An electronic device (e.g., integrated circuit) and method of making the electronic device is provided that reduces a strength of an electric field generated outside a package of the electronic device proximate to the low voltage lead pins. The electronic device includes a low voltage side and a high voltage side. The low voltage side includes a low voltage die attached to a low voltage die attach pad. Similarly, the high voltage side includes a high voltage die attached to a high voltage die attach pad. Lead pins are attached to each of the low and high voltage attach pads and extend out from a package of the electronic device in an inverted direction.

Abstract: A digital input receiver system comprises a first input receiver having a first current limiter input, and a first voltage comparator input coupled to a first node. A first resistor is coupled between the first node and the first current limiter input. The first input receiver outputs a digital logic signal and is coupled to a second node. The receiver system further comprises a second input receiver having a second current limiter input, and a second voltage comparator input coupled to the second node. A second resistor is coupled between the second node and the second current limiter input. The second input receiver outputs a malfunction signal. The first and second input receivers are configured to limit current through the receiver system to less than an overcurrent threshold of the first and second input receivers.

Abstract: The disclosure provides a sample adaptive offset (SAO) encoder. The SAO encoder includes a statistics collection (SC) block and a rate distortion optimization (RDO) block coupled to the SC block. The SC block receives a set of deblocked pixels and a set of original pixels. The SC block categorizes each deblocked pixel of the set of deblocked pixels in at least one of a plurality of band and edge categories. The SC block estimates an error in each category as difference between a deblocked pixel of the set of deblocked pixels and corresponding original pixel of the set of original pixels. The RDO block determines a set of candidate offsets associated with each category and selects a candidate offset with a minimum RD cost. The minimum RD cost is used by a SAO type block and a decision block to generate final offsets for the SAO encoder.

Abstract: In described examples, a device mounted on a substrate includes an encapsulant. In at least one example, an encapsulant barrier is deposited along a scribe line, along which the substrate is singulatable. To encapsulate one or more terminals of the substrate, an encapsulant is deposited between the encapsulant barrier and an edge of the device parallel to the encapsulant barrier.

Abstract: An integrated microfabricated sensor includes a sensor cell having a cell body, a first window attached to the cell body, and a second window attached to the cell body. The cell body laterally surrounds a cavity, so that both windows are exposed to the cavity. The sensor cell contains a sensor fluid material in the cavity. The cavity has concave profiles at cell body walls, so that the cavity is wider in a central region, approximately midway between the first window and the second window, than at the first surface and at the second surface. The cell body walls of the cell body have acute interior angles at both windows. The cell body is formed using an etch process that removes material from the cell body concurrently at the first surface and the second surface, forming the acute interior angles at both the first surface and the second surface.

Abstract: An integrated circuit containing a first plurality of MOS transistors operating in a low voltage range, and a second plurality of MOS transistors operating in a mid voltage range, may also include a high-voltage MOS transistor which operates in a third voltage range significantly higher than the low and mid voltage ranges, for example 20 to 30 volts. The high-voltage MOS transistor has a closed loop configuration, in which a drain region is surrounded by a gate, which is in turn surrounded by a source region, so that the gate does not overlap field oxide. The integrated circuit may include an n-channel version of the high-voltage MOS transistor and/or a p-channel version of the high-voltage MOS transistor. Implanted regions of the n-channel version and the p-channel version are formed concurrently with implanted regions in the first and second pluralities of MOS transistors.

Abstract: Virtual boundary processing in adaptive loop filtering (ALF) requires that padded values be substituted for unavailable pixel rows outside the virtual boundaries. Methods and apparatus are provided for virtual boundary processing in ALF that allow the use of more actual pixel values for padding than in the prior art.

Abstract: A method for luma-based chroma intra-prediction in a video encoder or a video decoder is provided that includes filtering reconstructed neighboring samples of a reconstructed down sampled luma block, computing parameters ? and ? of a linear model using the filtered, reconstructed neighboring samples of the reconstructed down sampled luma block and reconstructed neighboring samples of a corresponding chroma block, wherein the linear model is PredC[x, y]=?·RecL?[x, y]+?, wherein x and y are sample coordinates, PredC is predicted chroma samples, and RecL? is samples of the reconstructed down sampled luma block, and computing samples of a predicted chroma block from corresponding samples of the reconstructed down sampled luma block using the linear model and the parameters.

Abstract: An example apparatus includes: a signal terminal for inputting a signal or for outputting a signal; functional circuitry coupled to the signal terminal; a positive supply rail for supplying a positive voltage; a ground supply rail for supplying a ground voltage; a first electrostatic discharge protection circuit coupled between the positive supply rail and the ground supply rail; a second electrostatic discharge protection circuit coupled between the signal terminal and the ground supply rail; an enable circuit coupled to the signal terminal and to the positive supply rail; and a common trigger circuit having a trigger output signal coupled to the first electrostatic discharge protection circuit and to the second electrostatic discharge protection circuit. Additional apparatus and methods are disclosed.