Abstract: A field effect transistor (FET) engager, for example, includes electrically coupling a gate driver to a gate of a FET for testing the FET. The FET engager further includes providing a probe pad for test instrument measurement of the FET without test instrument capacitance impacting operation of the FET. The FET engager can electrically couple to the gate of the FET hold the gate of the FET at a low voltage while the source and drains are stress tested. The FET engager provides fail-safe mechanisms against accidental turn-on of the FET during operation. The FET engager can provide a second probe pad for selective test instrument turn-on of a second FET. The FET engager can allow test instrument measurement of gate current of the FET without test instrument capacitance impacting operation of the FET.

Abstract: In some examples, a system comprises a nuclear event detector (NED) to issue a nuclear event status signal, a primary power supply to issue a power status signal, a backup power supply, a non-volatile storage, and a processor coupled to the non-volatile storage and the NED and switchably coupled to the primary and backup power supplies. The processor is to store a state of the processor to the non-volatile storage based on the nuclear event status signal, and the processor is to selectively receive power from either the primary power supply or the backup power supply based on the nuclear event status signal and the power status signal.

Abstract: A functional safety POR system requires implementing voltage detectors and supervisory functions in a complex SOC. These features are implemented within the SOC without external components. Three stages of voltage monitoring are implemented to ensure redundancy.

Abstract: A voltage regulator (such as a low drop-out regulator) includes a pass transistor coupled to an input voltage node and an output voltage node. The voltage regulator also includes a drive transistor coupled to a control input of the pass transistor and a first resistor coupled between a source and a back gate of the drive transistor. The voltage regulator also includes a complementary to absolute temperature (CTAT) current generator circuit coupled to the resistor and configured to generate a CTAT current to bias the first resistor.

Abstract: In the proposed low complexity technique a hierarchical approach is created. An initial FFT based detection and range estimation gives a coarse range estimate of a group of objects within the Rayleigh limit or with varying sizes resulting from widely varying reflection strengths. For each group of detected peaks, demodulate the input to near DC, filter out other peaks (or other object groups) and decimate the signal to reduce the data size. Then perform super-resolution methods on this limited data size. The resulting distance estimations provide distance relative to the coarse estimation from the FFT processing.

Abstract: Disclosed examples include battery apparatus and balancing circuits for transferring charge between one or more of a plurality of battery cells and a second battery, in which a battery is coupled with a first winding of a transformer, and the second battery is coupled with a second transformer winding. A first transistor is turned on to allow current flow in the first winding to discharge the first battery, and then the first transistor is turned off. The resulting induced voltage in the second winding turns on a second transistor to provide flyback active charge balancing to charge the second battery. A signal from the third winding allows detection of low or zero current flow in the second winding for a controller to begin subsequent charge transfer cycles for full isolation between the first and second batteries.

Abstract: A system comprises a buffer circuit coupled to a comparator, and an adaptive threshold control circuit coupled to a timer and comparator. Buffer circuit receives a first voltage across a control terminal and a first current terminal of a transistor and a second voltage across a second current terminal and the first current terminal of the transistor. Comparator compares first voltage to a first threshold, generating a first trigger signal when it crosses first threshold, and compares second voltage to a second threshold, generating a second trigger signal when it crosses second threshold. Timer determines length of time between trigger signals. Adaptive threshold control circuit generates a first control signal for first trigger signal, and a second control signal for second trigger signal, and provides a control signal to comparator indicative of whether length of time is greater than or less than user-programmed value, causing comparator to adjust first threshold.

Abstract: Described herein is a technology or a method for pre-fabricating pre-cut plating lines on a lead frame with use of a pre-cut etchback process to minimize burrs during a semiconductor package singulation process. A package includes: a chip, and a lead frame that mounts the chip. The lead frame further includes pre-fabricated pre-cut plating lines that are etched back on the lead frame to form an opening slot on a periphery of the lead frame. The opening slot allows a saw blade to cut through a prepreg material, without touching or cutting a conductive material of the lead frame.

Abstract: A wakeup circuit includes an energy detection circuit and a wakeup signal generation circuit coupled to the energy detection circuit. The energy detection circuit is configured to, in response to receiving an input signal, generate a detect signal that is proportional to the input signal. The energy detection circuit is powered by the input signal. The wakeup signal generation circuit is configured to, in response to receiving the detect signal, generate a wakeup signal.

Abstract: Multi-Nyquist differentiator circuits and a radio frequency sampling receiver that applies a multi-Nyquist differentiator circuit. A multi-Nyquist differentiator includes a fixed coefficient filter, a scaling circuit, and a summation circuit. The fixed coefficient filter is configured to filter digital samples generated by an ADC. The scaling circuit is coupled to an output of the fixed coefficient filter, and is configured to scale output of the fixed coefficient filter based on a selected Nyquist band. The summation circuit is coupled to the scaling circuit, and is configured to generate a derivative of the digital samples based on output of the scaling circuit.

Abstract: Several methods and systems for encoding pictures are disclosed. In an embodiment, a method comprises dividing an LCU of a picture into a plurality of MERs having size equal to or less than a predetermined size. For one or more MERs of the plurality of MERs, a number of first motion searches are performed for determining a first quad-tree based on a cost function associated with a first plurality of PUs of the one or more MERs. A number of second motion searches are performed for the LCU, for determining a second quad-tree, based on the cost function associated with a second plurality of PUs of the LCU. The first quad-tree or the second quad-tree is selected for performing encoding of the picture based on a comparison of a first cost of the first quad-tree with a second cost of the second quad-tree.

Abstract: This disclosure describes techniques for performing semi-global matching (SGM) path cost compression. In some examples, the techniques may perform disparity-dependent sub-sampling of a set of SGM path costs where the sub-sampling ratio is determined based on a candidate disparity level. The sub-sampled SGM path costs may be stored in a memory. When retrieved from memory, the sub-sampled SGM path costs may be interpolated to reconstruct the other path costs not stored in the memory. The reconstructed path costs may be used for further SGM processing. In further examples, the techniques may perform disparity-dependent quantization on the SGM path costs or the sub-sampled SGM path costs, and store the quantized SGM path costs in memory. The techniques of this disclosure may reduce bandwidth as well as reduce the memory footprint needed to implement an SGM algorithm.

Abstract: A system comprises a DC-to-DC voltage converter, the DC-to-DC voltage converter comprising: a high-side FET comprising a gate, a source, and a drain; a node coupled to the source of the high-side FET; a low-side FET comprising a gate, a source, and a drain coupled to the node; and a controller coupled to the gate of the high-side FET to switch on and off the high-side FET, and coupled to the gate of the low-side FET to switch on and off the low-side FET, the controller configured to switch on the low-side FET for a time interval before switching on the high-side FET and to switch off the low-side FET before switching on the high-side FET.

Abstract: In described examples, a cavity is formed between a substrate and a cap. One or more access holes are formed through the cap for removing portions of a sacrificial layer from within the cavity. A cover is supported by the cap, where the cover is for occulting the one or more access holes along a perspective. An encapsulant seals the cavity, where the encapsulant encapsulates the cover and the one or more access holes.

Abstract: Acoustic wave resonators having Fresnel features are disclosed. An example integrated circuit package includes an acoustic wave resonator, the acoustic wave resonator including a Fresnel surface. In some examples, the Fresnel surface includes a plurality of recessed features and/or protruding features at different locations on the Fresnel surface, each of the plurality of features to confine main mode acoustic energy from a respective portion of the Fresnel surface in a central portion of the acoustic wave resonator.

Abstract: A processor with fault generating circuitry responsive to detecting a processor write is to a stack location that is write protected, such as for storing a return address at the stack location.

Abstract: Described example aspects include an integrated circuit includes a timing controller configured to select a selected time slot in a measurement period having a plurality of time slots and a transmit driver configured to provide a transmit signal in accordance with the selected time slot, in which the transmit signal is transmitted to an optical transmitter. The integrated circuit also includes a range estimator configured to receive a received signal after the selected time slot from an optical receiver that is configured to receive a reflection of light transmitted by the optical transmitter off an object, the range estimator configured to determine an estimated distance of the object based on the received signal.

Abstract: A specialized low drop-out voltage regulator (LDO) computer system stores a generalized base model of an LDO. The base model includes values representing a circuit topology and a set of analog behavior blocks associated with the generalized LDO. Values of a set of operational parameters associated with a specific model of LDO are input to the specialized LDO computer system from a data sheet associated with the specific model of LDO. The specialized LDO computer system transforms the set of operational parameters into a computer model of the specific LDO. The LDO-specific computer model is output as a netlist or as a set of instantiation control values to control external hardware such as an integrated circuit die tooling system or a computer graphical display system.

Abstract: This disclosure describes a novel method and apparatus for testing TSVs within a semiconductor device. According to embodiments illustrated and described in the disclosure, a TSV may be tested by stimulating and measuring a response from a first end of a TSV while the second end of the TSV held at ground potential. Multiple TSVs within the semiconductor device may be tested in parallel to reduce the TSV testing time according to the disclosure.

Abstract: A digital system has a dielectric core waveguide that has a longitudinal dielectric core member. The core member has a body portion and a transition region, with a cladding surrounding the dielectric core member. The body portion of the core member has a first dielectric constant. The transition region of the core member has a graduated dielectric constant value that gradually changes from the first dielectric constant value adjacent the body portion to a third dielectric constant.