Abstract: The disclosure provides an amplifier. The amplifier includes a first transistor that receives a first input and generates a first load current. A first output node is coupled to a power supply through a first load resistor. The first load resistor receives the first load current. A first capacitor network is coupled to the first output node and draws a first capacitive current from the first output node. A first current buffer is coupled between the first output node and the first transistor. A current through the first current buffer is a summation of the first load current and the first capacitive current.

Abstract: According to an embodiment, a bipolar transistor is disclosed for Electrostatic discharge (ESD) management in integrated circuits. The bipolar transistor enables vertical current flow in a bipolar transistor cell configured for ESD protection. The bipolar transistor includes a selectively embedded P-type floating buried layer (PBL). The floating P-region is added in a standard NPN cell. During an ESD event, the base of the bipolar transistor extends to the floating P-region with a very small amount of current. The PBL layer can provide more holes to support the current resulting in decreased holding voltage of the bipolar transistor. With the selective addition of floating P-region, the current scalability of the bipolar transistor at longer pulse widths can be significantly improved.

Abstract: An integrated circuit includes a capacitor located over a semiconductor substrate. The capacitor includes a first conductive layer having a first lateral perimeter, and a second conductive layer having a second smaller lateral perimeter. A first dielectric layer is located between the second conductive layer and the first conductive layer. The first dielectric layer has a thinner portion having the first lateral perimeter and a thicker portion having the second lateral perimeter. An interconnect line is located over the substrate, and includes a third conductive layer that is about coplanar with and has about a same thickness as the first conductive layer. A second dielectric layer is located over the third conductive layer. The second dielectric layer is about coplanar with and has about a same thickness as the thinner portion of the first dielectric layer.

Abstract: A device includes a first transistor coupled to a ground node and a current source. The first transistor includes a control terminal coupled to a reference voltage source, where the current source is coupled to an input voltage source. The device includes a second transistor coupled to the input voltage source, where the second transistor includes a control terminal coupled to the first transistor. The device includes a third transistor coupled to the second transistor, where the third transistor includes a control terminal coupled to an output voltage node. The device includes a fourth transistor coupled to the third transistor, where the fourth transistor includes a control terminal coupled to the output voltage node. The device includes a fifth transistor coupled to the fourth transistor and a resistor, where the fifth transistor includes a control terminal coupled to the fourth transistor. The resistor is coupled to the ground node.

Abstract: A cell balancing system includes sensing circuitry configured to sense a cell voltage of each of a plurality of cells of a battery. Cell balancing circuitry is configured to balance each of the plurality of cells in response to a respective cell balancing command for each of the plurality of cells. A comparison circuit configured to compare the sensed cell voltages for each of the plurality of cells to an adaptive threshold voltage. The comparison circuit generates a respective cell state for each of the plurality of cells to indicate a state of the respective cell voltage for each of the plurality of cells relative to the adaptive threshold voltage. A controller is configured to set the respective cell balancing command for each of the plurality of cells and to adjust the adaptive threshold voltage based on an evaluation of the cell states for the plurality of cells.

Abstract: In described examples of circuitry and methods for testing multiple memories, a controller generates a sequence of commands to be applied to one or more of the memories, where each given command includes expected data, and a command address. Local adapters are individually coupled with the controller and with an associated memory. Each local adapter translates the command to a memory type of the associated memory, maps the command address to a local address of the associated memory, and provides test results to the controller according to read data from the local address of the associated memory and the expected data of the command.

Abstract: Disclosed examples include self-biased DLL circuits to generate a bias current signal proportional to a repetition frequency of a first signal representing continuous switching or discontinued switching operation of the DC-DC converter. The DLL circuit includes a monostable multivibrator to provide a pulse output signal in response to an edge of the first signal with a pulse duration set by a control current signal, a phase detector to provide output signals according to a phase difference between an edge of the pulse output signal and the first signal, and an output circuit to provide an output signal according to the phase detector output signals and according to an offset signal, to provide the bias current signal according to the output signal, and to provide the control current signal according to the output signal.

Abstract: Data memory protection is provided for a signal processing system such as a radar system in which the data memory is protected with a common set of parity bits rather than requiring a set of parity bits for each memory word as in Error Correction Coded (ECC) memories. The common set of parity bits may be updated as memory words in the data memory are accessed as part of signal processing of one or more digital signals. The memory protection ensures that in the absence of memory errors the common parity bits are zero at the end of processing the digital signals as long as each word in the data memory that is used for storing the signal processing data is written and read an equal number of times.

Abstract: Methods for monitoring of performance parameters of one or more receive channels and/or one or more transmit channels of a radar system-on-a-chip (SOC) are provided. The radar SOC may include a loopback path coupling at least one transmit channel to at least one receive channel to provide a test signal from the at least one transmit channel to the at least one receive channel when the radar SOC is operated in test mode. In some embodiments, the loopback path includes a combiner coupled to each of one or more transmit channels, a splitter coupled to each of one or more receive channels, and a single wire coupling an output of the combiner to an input of the splitter.

Abstract: In methods, apparatus, systems, and articles of manufacture to a high efficient hybrid power converter, an example apparatus includes: a switched capacitor (SC) converter to generate a first voltage based on a voltage source; and a direct current-to-direct current (DC-DC) converter to generate a second voltage based on the voltage source of the apparatus, the difference between the first voltage and the second voltage corresponding to an output voltage.

Abstract: Methods and apparatus for using two stage ultrasonic lens cleaning for water removal are disclosed. An apparatus can expel fluid from a droplet on an optical surface using an ultrasonic transducer mechanically coupled to the optical surface and having first and second resonant frequency bands. A signal generator can generate a first signal including a first frequency to be coupled with the ultrasonic transducer mechanically coupled to the surface, and can generate a second signal including a second frequency to be coupled with the ultrasonic transducer mechanically coupled to the surface. Switching circuitry can activate the ultrasonic transducer at the first frequency to reduce the droplet from a first size to a second size, and to activate the ultrasonic transducer at the second frequency to reduce the droplet from the second size to a third size.

Abstract: Disclosed embodiments include a processing device having a debug controller that issues a context-sensitive debug request. The context-sensitive debug request includes at least one conditional criteria. A processing core receives the debug request, determines whether all of the at least one conditional criteria are true, and services the debug request when all of the at least one conditional criteria are true by accessing a data location indicated in the debug request. The servicing of the debug request may be performed in real-time mode without suspending the processing device, and the accessing can be a read or a write operation depending on the type of access indicated in the debug request. The conditional criteria may include one or more of a processor mode condition, a virtual machine identifier condition, and a debug context condition.

Abstract: Methods, systems, and apparatus to increase common-mode transient immunity in isolation devices is disclosed. An example apparatus includes a current mirror including an input terminal and an output terminal; a transistor including a gate terminal, a first current terminal, and a second current terminal, the gate terminal coupled to a reference voltage terminal, the first current terminal coupled to the input terminal of the current mirror, and the second current terminal coupled to an input node; a buffer including an input terminal and an output terminal, the input terminal of the buffer coupled to the output terminal of the current mirror; and a logic gate including an input terminal and an output terminal, the input terminal of the logic gate coupled to the output terminal of the buffer.

Abstract: A leadframe includes a first die attach pad (“DAP”) having a first longitudinally extending edge surface and a second DAP having a first longitudinally extending edge surface. The second DAP is positioned with the first longitudinally extending edge surface thereof in adjacent, laterally and vertically spaced relationship with the first longitudinally extending edge surface of the first DAP.

Abstract: A stream of data is accessed from a memory system using a stream of addresses generated in a first mode of operating a streaming engine in response to executing a first stream instruction. A block cache management operation is performed on a cache in the memory using a block of addresses generated in a second mode of operating the streaming engine in response to executing a second stream instruction.

Abstract: A method for interpreting clicks on a multi-function input device included in a digital device is provided that includes receiving a click from the multi-function input device, determining a position of the click on the multi-function input device and a cursor displayed on a display comprised in the digital device, performing an action according to the position of the click when the cursor is a cursor designated as a cursor requiring a click at a specific position on the multi-function input device, and performing an action associated with the cursor when the cursor is a not a cursor designated as a cursor requiring a click at a specific position on the multi-function input device. A digital device is also provided that includes a multi-function input device, a display, a memory storing software instructions for performing the method, and a processor to execute the software instructions.

Abstract: Error correction code (ECC) hardware includes write generation (Gen) ECC logic and a check ECC block coupled to an ECC output of a memory circuit with read Gen ECC logic coupled to an XOR circuit that outputs a syndrome signal to a syndrome decode block coupled to a single bit error correction block. A first MUX receives the write data is in series with an input to the write Gen ECC logic or a second MUX receives the read data from the memory circuit in series with an input of the read Gen ECC logic A cross-coupling connector couples the read data from the memory circuit to a second input of the first MUX or for coupling the write data to a second input of the second MUX. An ECC bit comparator compares an output of the write Gen ECC logic to the read Gen ECC logic output.

Abstract: Described examples include a projection device having a light source. The projection device also has a spatial light modulator arranged to receive light from the light source and provide modulated light. The projection device also has projection optics arranged to receive and project the modulated light. The projection device also has a field splitting element between the spatial light modulator and the projection optics, a first portion of the field splitting element being structured to pass at least a first portion of the modulated light to the projection optics for projection at a first focal length, and a second portion of the field splitting element being structured to pass at least a second portion of the modulated light to the projection optics for projection at a second focal length.

Abstract: An apparatus for mitigating contamination of an optical device comprises an open-topped, closed-sided, and closed-bottomed housing cup partially defining a protected volume to enclose the optical device. A housing cap encloses a top of the housing cup and partially defines the protected volume. The housing cap includes a top collar having an open central aperture. The top collar includes at least one drain channel extending longitudinally downward into a top collar top surface and extending across the top collar top surface laterally outward from the central aperture. A top cover laterally spans the central aperture of the top collar. An interface structure circumscribes the top cover to suspend the top cover downwardly into the housing cup from the top collar. The interface structure prevents direct contact between the top cover and the top collar.

Abstract: In described examples, a sawtooth waveform generator generates a sawtooth waveform having a first rise time. A comb waveform circuit has a power terminal coupled to receive the sawtooth waveform from an output of the sawtooth waveform generator. The comb waveform circuit generates a comb waveform in response to the sawtooth waveform. The comb waveform has a second rise time that is faster than the first rise time.