Abstract: An integrated circuit chip includes a bimodal power N-P-Laterally Diffused Metal Oxide Semiconductor (LDMOS) device having an N-gate coupled to receive an input signal and a level shifter coupled to receive the input signal and to provide a control signal to a P-gate driver of the N-P-LDMOS device. A method of operating an N-P-LDMOS power device is also disclosed.

Abstract: One example includes a current measurement system. The system includes at least two magnetic field sensors positioned proximal to and in a predetermined arrangement with respect to a current conductor, each of the magnetic field sensors being configured to measure magnetic field associated with a current flowing in the current conductor and provide respective magnetic field measurements. The system also includes a current measurement processor configured to implement a mathematical algorithm based on a Taylor series expansion of the magnetic field measurements to calculate an amplitude of the current based on the mathematical algorithm.

Abstract: A modulator of an analog to digital converter includes a quantizer component configured to generate a digital signal based on a clock input operating at a sample rate. The modulator further includes a first digital to analog converter (DAC) configured to generate first DAC output at half the sample rate. The modulator further includes a second DAC configured to generate second DAC output at half the sample rate, where the first DAC and the second DAC are updated at alternate cycles of the clock input.

Abstract: In described examples, an isolated DC-DC converter includes: an input node for receiving an input voltage; a transformer including first and second terminals; first and second low-side switches; and first and second high-side switches. The first low-side switch is coupled between the first terminal and a primary side ground. The second low-side switch is coupled between the second terminal and the primary side ground. The first high-side switch is coupled between the first terminal and the input node and is configured to be activated by a voltage at the second terminal. The second high-side switch is coupled between the second terminal and the input node and is configured to be activated by a voltage at the first terminal. Further, the isolated DC-DC converter includes a switch controller to cause the first and second voltages to alternatingly be zero by opening and closing the first and second low-side switches.

Abstract: A semiconductor device includes an integrated circuit attached to a chip carrier in a flip chip configuration. A substrate extends to a back surface of the integrated circuit, and an interconnect region extends to a front surface of the integrated circuit. A substrate bond pad is disposed at the front surface, and is electrically coupled through the interconnect region to the semiconductor material. The chip carrier includes a substrate lead at a front surface of the chip carrier. The substrate lead is electrically coupled to the substrate bond pad. An electrically conductive compression sheet is disposed on the back surface of the integrated circuit, with lower compression tips making electrical contact with the semiconductor material in the substrate. The electrically conductive compression sheet is electrically coupled to the substrate lead of the chip carrier by a back surface shunt disposed outside of the integrated circuit.

Abstract: A WLAN device includes a processor implementing a MAC layer and a PHY layer which is coupled to a transceiver including a receive (Rx) chain and a transmit (Tx) chain that is coupled to an antenna. A preamble decode-based receive suspend algorithm has software stored in a memory that is implemented by the processor or by hardware including digital logic. The algorithm responsive to receiving a packet including a Physical Layer Convergence Protocol (PLCP) header, a MAC header, and data, is for analyzing a length field in the PLCP header to determine whether the packet is an undesignated packet and whether there is sufficient time remaining for implementing a turning off and then back on of an analog portion of the Rx chain to avoid missing a next packet. If the undesignated packet and sufficient time are present, the analog portion of the Rx chain is turned off.

Abstract: Described examples include a projector including a first prism having a dichroic layer. A second prism has a first spatial light modulator on a first surface, and a first light source directed through a second surface of the second prism to the first spatial light modulator. The first spatial light modulator is operable to modulate the first light to provide modulated first light that is reflected off the second surface of the second prism and the dichroic layer to projection optics. A third prism has a second spatial light modulator on a first surface and a second light source directed through a second surface to the second spatial light modulator. The second spatial light modulator is operable to modulate the second light to provide modulated second light that is reflected off the second surface of the third prism and passes through the dichroic layer to the projection optics.

Abstract: Packaged electronic devices and integrated circuits include a ceramic material or other thermally conductive, electrically insulating substrate with a patterned electrically conductive feature on a first side, and an electrically conductive layer on a second side. The IC further includes a semiconductor die mounted to the substrate, the semiconductor die including an electrically conductive contact structure, and an electronic component, with an electrically insulating lamination structure enclosing the semiconductor die, the frame and the thermal transfer structure. A redistribution layer with a conductive structure is electrically connected to the electrically conductive contact structure.

Abstract: In circuitry for measuring a voltage at a node, a capacitive divider is coupled to the node, wherein the capacitive divider provides a first output. A resistive divider is coupled to the node, wherein the resistive divider provides a second output.

Abstract: A system for error correction code (ECC) management of write-once memory (WOM) codes includes, for example, a controller for selecting between one of a WOM (Write-Once Memory) mode and an ECC (error correction code) mode. A codec is arranged to operate in the selected mode. The codec while operating in the ECC mode is arranged to identify a bit position of at least one bit error in response to ECC parity bits of a first received data word. The codec while operating in the WOM mode is arranged to receive a WOM-encoded word from an addressed location in a WOM device, to receive a second received data word to be encoded and written to the addressed location, and to generate WOM-encoded word for writing to the addressed location in the WOM device. The WOM-encoded word for writing to the addressed location is optionally ECC encoded.

Abstract: A method for forming a graphene FET includes providing a graphene layer having a surface. A first metal layer having a work function <4.3 eV is deposited on the graphene surface. The first metal layer is oxidized to form a first metal oxide layer. The first metal oxide layer is etched to provide open surface contact regions including a first and a second region of the graphene layer for providing a graphene surface source and drain contact. A second metal layer is deposited including a second metal layer portion providing a source with a source contact over the graphene surface source contact and a second metal layer portion providing a drain with a drain contact over the graphene surface drain contact. A grown-in graphitic interface layer is formed at an interface between the source contact and graphene surface source contact and the drain contact and graphene surface drain contact.

Abstract: A controller for driving a motor includes a multiphase driver, an analog-to-digital converter (ADC), impedance estimation circuitry, and fault detection circuitry. The multiphase driver is configured to generate drive signals for energizing each motor phase winding. The ADC is configured to digitize voltage and current from each motor phase winding. The impedance estimation circuitry is configured to determine a phasor value for the digitized voltages and for the digitized currents at a predetermined harmonic frequency, and to determine a sequence impedance value based on the phasor values. The fault detection circuitry is configured to identify a fault in the windings of the motor based on the sequence impedance value.

Abstract: The disclosure describes a novel method and apparatus for improving silicon interposers to include test circuitry for testing stacked die mounted on the interposer. The improvement allows for the stacked die to be selectively tested by an external tester or by the test circuitry included in the interposer.

Abstract: An integrated circuit contains a logic MOS transistor and a memory MOS transistor of a same polarity. The logic MOS transistor has a logic channel stop layer. The memory MOS transistor has a memory channel stop layer. An average dopant density of the memory channel stop layer is higher than an average dopant density of the logic channel stop layer. The integrated circuit is formed by forming a global mask which exposes both the logic and memory MOS transistors. A global channel stop dose of dopants is implanted in the logic and memory MOS transistors. A memory mask is formed which exposes the memory MOS transistor and covers the logic MOS transistor. A memory channel stop dose of dopants of the same polarity is implanted into the memory MOS transistors. The memory channel stop dose of dopants is blocked from the logic MOS transistors.

Abstract: An electronic circuit includes an electronic device, an input/output terminal, and a protection device. The electronic device includes a signal terminal to receive an input signal. The input/output terminal is configured to receive the input signal from a source external to the electronic circuit. The protection device is coupled to the electronic device and to the input/output terminal. The protection device is configured to protect the electronic device from voltage of the input signal exceeding a threshold. The protection device includes a first semiconductor region, a first contact, and a second contact. The first contact connects the first semiconductor region to the input/output terminal. The second contact connects the first semiconductor region to the signal terminal of the electronic device.

Abstract: A system and method for enhanced channel hopping sequence is described. A pseudo random channel hopping sequence is redistributed using certain system specific parameters for separating adjacent transmission channels within a predetermined number of consecutive transmission channel numbers in the random channel hopping sequence to improve inter-channel interference between adjacent transmission channels.

Abstract: An apparatus to monitor and control a switching rate in a switch includes a differentiator circuit including a capacitor and a configurable resistor. The differentiator circuit further includes an input terminal of the capacitors configured to receive a first voltage from a switch and a differentiator node configured to receive a differentiated voltage based on the first voltage. The apparatus includes a peak detector circuit coupled to the differentiator node and configured to detect a peak value of the differentiated voltage. The apparatus further includes a driver circuit coupled to the peak detector circuit and configured to adjust a control signal to the switch responsive to the detected peak value of the differentiated voltage.

Abstract: Testing of integrated circuits is achieved by a test architecture utilizing a scan frame input shift register, a scan frame output shift register, a test controller, and a test interface comprising a scan input, a scan clock, a test enable, and a scan output. Scan frames input to the scan frame input shift register contain a test stimulus data section and a test command section. Scan frames output from the scan frame output shift register contain a test response data section and, optionally, a section for outputting other data. The command section of the input scan frame controls the test architecture to execute a desired test operation.

Abstract: A memory array comprising a word line and a bit line is disclosed. Each of a plurality of memory cells of the memory array has a first terminal connected to the bit line and a current path between the first terminal and a respective second terminal. A first memory cell of the plurality of memory cells has the second terminal coupled to receive a first supply voltage when selected by the word line. A second memory cell of the plurality of memory cells has the second terminal coupled to receive a voltage different from the first supply voltage when the first memory cell is selected by the word line.

Abstract: A laterally diffused metal oxide silicon (LDMOS) transistor and a method of making the LDMOS transistor are disclosed. The LDMOS transistor includes a drain drift region formed in a substrate and containing a drain contact region. A gate structure overlies a channel region in the substrate and a first shallow-trench isolation (STI) structure is formed between the drain contact region and the channel region. The first STI structure contains a high-k dielectric and a second STI structure contains silicon dioxide.