Abstract: A method of operating a wireless communication system (FIG. 4) is disclosed. The method includes receiving downlink control information (702) for transmission to a user equipment (UE) in enhanced physical downlink control channel (EPDCCH). A pseudo-random number generator is initialized (706) for generating a pseudo-random sequence. A plurality of demodulation reference signals (DMRS) are generated with the pseudo-random sequence. The plurality of DMRS is mapped with the EPDCCH and transmitted to the UE (712).

Abstract: In an example, a dual-phase inverting buck-boost power converter for use with at least first and second energy storage elements includes an inverting buck-boost power converter and an inverting boost converter. In an example, the inverting buck-boost power converter is coupled between an input node and an output node of the dual-phase inverting buck-boost power converter and includes a first plurality of switches operable to couple to the first energy storage element, wherein the inverting buck-boost power converter is operable to supply a first load current. In an example, the inverting boost converter is coupled in parallel with the inverting buck-boost power converter between the input node and the output node of the dual-phase inverting buck-boost power converter and includes a second plurality of switches operable to couple to the first and the second energy storage elements, wherein the inverting boost converter is operable to supply a second load current.

Abstract: First and second views of a stereoscopic image are received. In response to determining that the stereoscopic image has a predominance of foreground features, a convergence plane of the stereoscopic image is adjusted to improve a depth resolution of at least one foreground feature within the stereoscopic image for display to a human by a display device. In response to determining that the stereoscopic image has a predominance of background features, the convergence plane is adjusted to position at least most of the stereoscopic image as background features for display to the human by the display device.

Abstract: A thermoelectric device is disclosed which includes metal thermal terminals protruding from a top surface of an IC, connected to vertical thermally conductive conduits made of interconnect elements of the IC. Lateral thermoelectric elements are connected to the vertical conduits at one end and heatsinked to the IC substrate at the other end. The lateral thermoelectric elements are thermally isolated by interconnect dielectric materials on the top side and field oxide on the bottom side. When operated in a generator mode, the metal thermal terminals are connected to a heat source and the IC substrate is connected to a heat sink. Thermal power flows through the vertical conduits to the lateral thermoelectric elements, which generate an electrical potential. The electrical potential may be applied to a component or circuit in the IC. The thermoelectric device may be integrated into an IC without adding fabrication cost or complexity.

Abstract: Methods and apparatus to calibrate micro-electromechanical systems are disclosed. An pressure sensor calibration apparatus includes a pressure chamber in which a first pressure sensor is to be disposed; one or more first sensors to measure a first capacitance value from the first pressure sensor from a physical test performed; the one or more first sensors to measure a second capacitance value from a first electrical test performed on the first pressure sensor; and a correlator to determine correlation coefficient values based on the first capacitance value determined during the physical test on the first pressure sensor and the second capacitance value determined during the first electrical test on the first pressure sensor; and a calibrator to determine calibration coefficient values to calibrate a second pressure sensor based on the correlation coefficient values and a third capacitance value determined during a second electrical test on the second pressure sensor.

Abstract: An encapsulated package is provided that includes a pair integrated circuit (IC) die. A radio frequency (RF) circuit on one of the IC die is operable to transmit an RF signal having a selected frequency. An RF circuit on the other IC die is operable to receive the RF signal Encapsulation material encapsulates the IC die. A photonic waveguide couples between the RF transmitter and RF receiver to form galvanic path isolation between the two IC die. The photonic waveguide is formed by a photonic structure within the encapsulation material.

Abstract: A wakeup circuit includes an amplification stage circuit and a filter stage circuit. The amplification stage circuit is configured to, in response to receiving an input signal, generate an amplified digital signal that is proportional to the input signal. The filter stage circuit is configured to, in response to receiving a threshold number of toggles of the amplified digital signal within a pre-defined time period (such as one clock period of a clock signal), generate a wakeup signal as an output signal of the filter stage circuit.

Abstract: A comparator circuit includes a first transistor configured to receive a first input and a second transistor configured to receive a second input. The comparator circuit further includes a third transistor coupled to a terminal of each of the first and second transistors. The third transistor is configured to be controlled by a first control signal. A gate of a fifth transistor is coupled to a terminal of a fourth transistor at a first node and a gate of the fourth transistor is coupled to a terminal of the fifth transistor at a second node. A sixth transistor is coupled between the first and fourth transistors. A seventh transistor is coupled between the second and fifth transistors. A gate of the sixth transistor and a gate of the seventh transistor are coupled together at a fixed voltage level.

Abstract: Methods are provided for reducing the size of a transpose buffer used for computation of a two-dimensional (2D) separable transform. Scaling factors and clip bit widths determined for a particular transpose buffer size and the expected transform sizes are used to reduce the size of the intermediate results of applying the 2D separable transform. The reduced bit widths of the intermediate results may vary across the intermediate results. In some embodiments, the scaling factors and associated clip bit widths may be adapted during encoding.

Abstract: A sheet of electronic components includes a plurality of electronic components. A plurality of connecting members mechanically connects the electronic components together. A first fiducial marker is located at a first predetermined location on the sheet and a second fiducial marker is located at a second predetermined location on the sheet.

Abstract: A dual-PFD circuit with delay feedback generated by a dual-modulus prescaler based on mode control from a feedback delay generation circuit. The PFD circuit can be used with a PLL feedback divider to divide a VCO clock signal VCO_clk and generate FB and FB_DLY signals. The PLL feedback divider includes a dual modulus prescaler to selectively divide the VCO_clk by either M or M+1 (such as 4/5) based on a divide mode control input to generate a prescaled divide signal, and a programmed counter/divider (N counter/1/N divider) to selectively divide the prescaled divide signal to generate the FB signal, and a delay generation circuit to selectively delay the FB signal by a pre-defined delay to generate the FB_DLY signal. The prescaler is responsive to the pre-defined delay from the delay generation circuit to change divide modes. The dual PFD circuit response to the FB and FB_DLY signals in relation to a reference signal to generate a phase comparison signal.

Abstract: A replacement metal gate transistor structure and method with thin silicon nitride sidewalls and with little or no high-k dielectric on the vertical sidewalls of the replacement gate transistor trench.

Abstract: An integrated circuit (IC) chip socket that can include a non-conductive housing and moveable pogo pins positioned within the non-conductive housing. The moveable pogo pins can include active pogo pins, each active pogo pin being positioned to a corresponding lead of an IC chip insertable into the IC chip socket. Moveable pogo pins can also include an inactive pogo pin positioned to avoid contacting each lead of the IC chip insertable into the IC chip socket.

Abstract: A method of fabricating integrated circuits (ICs) includes depositing a dielectric liner layer on a substrate including a semiconductor surface having a plurality of IC die formed therein each including functional circuitry including a plurality of interconnected transistors. A thin film resistor (TFR) layer including chromium (Cr) is deposited on the dielectric liner layer. The substrate is loaded into a hardmask layer deposition tool that includes a plasma source. The TFR layer is in-situ plasma pre-treated including flowing at least one inert gas and at least one oxidizing gas while in the hardmask layer deposition tool. A hardmask layer is deposited after the plasma pre-treating while remaining in the hardmask layer deposition tool. A pattern is formed on the hardmask layer, and the hardmask layer and TFR layer are etched stopping in the dielectric liner layer to form at least one resistor from the defined TFR layer.

Abstract: In described examples of methods and control circuitry to control a power conversion system, a regulator circuit is coupled to provide switching control signals according to a regulation signal to operate a plurality of converter switches to generate a voltage signal at a switching node. A compensation sense circuit is coupled to provide a compensation pulse signal having a duty cycle that represents a percentage of time that a current flowing through the switching node is above a threshold value. A current compensation circuit adjusts the regulation signal according to the compensation pulse signal.

Abstract: Methods and apparatus for providing a time-interleaved current-feedback droop function for multiphase buck converters. An example method includes outputting a first control signal to enable a first set of switches corresponding to a first voltage of a first phase from a multiphase converter, the first phase included in a plurality of phases; enabling a first current associated with the first phase to be measured by a sample and hold circuit associated with the first phase; sampling the first current; holding the first current, the first current based on a load current for the first phase of the multiphase converter; and outputting a droop voltage based on a plurality of currents corresponding to the plurality of phases of the multiphase converter, the plurality of currents including the load current for the first phase.

Abstract: A semiconductor device includes a substrate having a semiconductor surface doped a second dopant type with a buried layer (BL) doped a first dopant type. First, second and third well regions doped the second dopant type are on top of the BL. Second doped regions doped the first dopant type on top of and contacting the BL arraigned as a first well ring and second well ring are around the first and third well regions respectively. At least one high-injection component including the first well region is surrounded by the first well ring. At least one component including the third well region is surrounded by the second well ring. An npn or pnp guard wall pocket including a wall of the first and second well rings, and the second well region is between the high-injection component and the component.

Abstract: A wireless power transfer system using a resonant rectifier circuit with capacitor sensing. A wireless power transfer system includes a power receiver resonant circuit and a synchronous rectifier. The power receiver resonant circuit includes an inductor and a capacitor connected in series with the inductor. The synchronous rectifier is configured to identify zero crossings of alternating current flowing through the inductor based on voltage across the capacitor, and control synchronous rectification of the alternating current based on timing of the zero crossings.

Abstract: In some examples, a system includes a first transistor comprising a first source terminal coupled to a first input terminal, a first drain terminal coupled to a first top plate sampling capacitor, and a first gate terminal. The system also includes a first input-dependent dual clock boost circuit coupled to the first input terminal via a first boost circuit input and to the first gate terminal via a first boost circuit output. The system further includes a second transistor comprising a second source terminal coupled to a second input terminal, a second drain terminal coupled to a second top plate sampling capacitor, and a second gate terminal. The system also includes a second input-dependent dual clock boost circuit coupled to the second input terminal via a second boost circuit input and to the second gate terminal of the second transistor via a second boost circuit output.

Abstract: In an embodiment, an adaptive drive strength switching converter includes a driver and a control loop coupled to the driver. In an embodiment, the control loop includes a peak detector, a comparator coupled to an output of the peak detector, a counter coupled to an output of the comparator, and a digital-to-analog converter (DAC) coupled to an output of the comparator.