Abstract: A high TCR tungsten resistor on a reverse biased Schottky diode. A high TCR tungsten resistor on an unsilicided polysilicon platform geometry. A high TCR tungsten resistor between two parallel polysilicon leads on remaining contact etch stop dielectric. A high TCR tungsten resistor embedded in a intermetal dielectric layer above a lower interconnect layer and below an upper interconnect layer. A method of forming a high TCR tungsten resistor on a reverse biased Schottky diode. A method of forming high TCR tungsten resistor on an unsilicided polysilicon platform geometry. A method of forming high TCR tungsten resistor between two parallel polysilicon leads on remaining contact etch stop dielectric. A method of forming high TCR tungsten resistor embedded in a inter metal dielectric layer above a lower interconnect layer and below an upper interconnect layer.

Abstract: A current sensing circuit includes a pass transistor, a first sense transistor, a second sense transistor, a driver circuit, and sense circuitry. The driver circuit coupled to, and configured to generate a drive signal to control, the pass transistor, the first sense transistor, and the second sense transistor. The sense circuitry coupled to the pass transistor, the first sense transistor, and the second sense transistor. The sense circuitry includes a first sense circuit and a second sense circuit. The first sense circuit is configured to generate an output current proportional to a current flowing in the pass transistor. The second sense circuit is coupled to the driver circuit and is configured to set the drive signal to a predetermined voltage responsive to a voltage across the pass transistor being less than a threshold voltage.

Abstract: An ESD cell includes an n+ buried layer (NBL) within a p-epi layer on a substrate. An outer deep trench isolation ring (outer DT ring) includes dielectric sidewalls having a deep n-type diffusion (DEEPN diffusion) ring (DEEPN ring) contacting the dielectric sidewall extending downward to the NBL. The DEEPN ring defines an enclosed p-epi region. A plurality of inner DT structures are within the enclosed p-epi region having dielectric sidewalls and DEEPN diffusions contacting the dielectric sidewalls extending downward from the topside surface to the NBL. The inner DT structures have a sufficiently small spacing with one another so that adjacent DEEPN diffusion regions overlap to form continuous wall of n-type material extending from a first side to a second side of the outer DT ring dividing the enclosed p-epi region into a first and second p-epi region. The first and second p-epi region are connected by the NBL.

Abstract: According to an embodiments, a system and method for managing electromagnetic interference in an electronic charging unit is disclosed. The operating frequencies of multiple electronic devices interfacing with the electronic charging unit may be dynamically altered to manage electromagnetic interference from each electronic device such that the aggregated electromagnetic interference from all electronic devices remains within predetermined limits.

Abstract: An amplifier includes an input stage, a folded cascode stage, and a class AB output stage. The folded cascode stage is coupled to the input stage. The class AB output stage is coupled to the folded cascode stage. The class AB output stage includes a high-side output transistor, a low-side output transistor, and a high-side feedback circuit that is coupled to the high-side output transistor. The high-side feedback circuit includes a high-side sense transistor and a high-side feedback transistor. The high-side sense transistor includes a control terminal that is coupled to a control terminal of the high-side output transistor. The high-side feedback transistor is coupled to an output of the high-side sense transistor and to the folded cascode stage. A first output of the folded cascode stage is coupled to the control terminal of the high-side sense transistor and to the control terminal of the high-side output transistor.

Abstract: An integrated circuit (IC) chip and method of booting the IC are disclosed. The method includes determining whether a boot pin configuration has been programmed and responsive to determining that the boot pin configuration has been programmed, performing a boot method indicated in a user-defined boot table. Responsive to determining that the boot pin configuration key has not been programmed, the method performs a boot method selected from a factory-defined boot table.

Abstract: Described examples include integrated circuits, drain extended transistors and fabrication methods therefor, including a multi-fingered transistor structure formed in an active region of a semiconductor substrate, in which a transistor drain finger is centered in a multi-finger transistor structure, a transistor body region laterally surrounds the transistor, an outer drift region laterally surrounds an active region of the semiconductor substrate, and one or more inactive or dummy structures are formed at lateral ends of the transistor finger structures.

Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements. A steam head register stores data elements next to be supplied to functional units for use as operands. An element duplication unit optionally duplicates data element an instruction specified number of times. A vector masking unit limits data elements received from the element duplication unit to least significant bits within an instruction specified vector length. If the vector length is less than a stream head register size, the vector masking unit stores all 0's in excess lanes of the stream head register (group duplication disabled) or stores duplicate copies of the least significant bits in excess lanes of the stream head register.

Abstract: In examples, a system comprises a differential amplifier coupled to a parasitic capacitor positioned between a first node and a first reference voltage source. The system comprises a buffer amplifier having an input terminal and an output terminal, the input terminal coupled to the first node and the output terminal coupled to a cancellation capacitor. The system includes a controlled current source coupled to the first node and the input terminal, the controlled current source coupled to a second reference voltage source. The system comprises a current sense circuit coupled to the cancellation capacitor and the second reference voltage source.

Abstract: Transmission of information in a wireless network is performed by allocating a channel from a transmitter to a receiver. The channel has at least one time slot with each time slot having a plurality of symbols. Each slot contains at least one reference symbol (RS). As information becomes available for transmission, it is classified as prioritized information (PI) and other information. One or more priority symbols are generated using the digital samples of the priority information. Other symbols are generated using the other data. Priority symbols are transmitted on the channel in a manner that separation of priority symbol(s) and a reference symbol does not exceed a time duration of one symbol. For example, Rank Indicator (RI) is transmitted using symbol k, ACKNAK is transmitted using symbol k+1; and the reference signal (RS) is transmitted using symbol k+2, wherein symbols k, k+1, and k+2 are consecutive in time. The other symbols are transmitted in available locations.

Abstract: The disclosure describes a process and apparatus for accessing devices on a substrate. The substrate may include only full pin JTAG devices (504), only reduced pin JTAG devices (506), or a mixture of both full pin and reduced pin JTAG devices. The access is accomplished using a single interface (502) between the substrate (408) and a JTAG controller (404). The access interface may be a wired interface or a wireless interface and may be used for JTAG based device testing, debugging, programming, or other type of JTAG based operation.

Abstract: In some examples, a sigma-delta analog-to-digital converter (ADC), comprises a first set of switches configured to receive a first voltage signal; a second set of switches coupled to the first set of switches at a first node and a second node, the second set of switches configured to receive a second voltage signal; an integrator including a first input sampling capacitor coupled to the first node and a second input sampling capacitor coupled to the second node, wherein the integrator configured to generate a first output signal. The sigma-delta ADC further comprises a comparator coupled to the integrator and configured to generate a second output signal based on the first output signal; and a controller unit having a first counter, a second counter, and a processor, the controller unit coupled to the first and second sets of switches, the integrator, and the comparator.

Abstract: A method of determining a summation of pixel characteristics for a rectangular region of a digital image includes determining if a base address for a data element in an integral image buffer is aligned for an SIMD operation by a processor embedded in an electronic assembly configured to perform Haar-like feature calculations. The data element represents a corner of the rectangular region of an integral image. The integral image is a representation of the digital image. The integral image is formed by data elements stored in the integral image buffer. The data element is loaded from the integral image buffer to the processor when the base address is aligned for the SIMD operation. An offset data element of an offset integral image is loaded from an offset integral buffer when the base address is non-aligned for the SIMD operation. The offset data element represents the corner of the rectangular region.

Abstract: An integrated fluxgate magnetic gradient sensor includes a common mode sensitive fluxgate magnetometer and a differential mode sensitive fluxgate magnetometer. The common mode sensitive fluxgate magnetometer includes a first core adjacent to a second core. The first and second cores are wrapped by a first excitation wire coil configured to receive an excitation current that affects a differential mode magnetic field. The differential mode sensitive fluxgate magnetometer includes a third core adjacent to the first core and a fourth core adjacent to the second core. The third and fourth cores are wrapped by a second excitation wire coil configured to receive an excitation current that affects a common mode magnetic field.

Abstract: An electrostatic discharge (ESD) protection circuit includes an active shunt transistor, a first pull-down transistor, and a second pull-down transistor. The active shunt transistor is coupled between a first I/O pad and a reference voltage. The first pull-down transistor is connected to the reference voltage. The second pull-down transistor is connected to the first pull-down transistor and the first I/O pad. The first pull-down transistor and the second pull-down transistor are in separate isolation tanks of an isolation deep n-well.

Abstract: In some embodiments, an apparatus comprises a semiconductor layer doped with a first-type dopant, a first region doped with the first-type dopant, a second region doped with the first-type dopant, and a third region doped with a second-type dopant, where the second-type dopant is opposite the first-type dopant. The first, second, and third regions are non-overlapping and are formed in the semiconductor layer. The third region is positioned between the first region and the second region. The apparatus also comprises a plurality of Zener implant regions buried in the semiconductor layer and the third region, where each of the plurality of Zener implant regions is configured to generate a different pinch-off region.

Abstract: A multi-phase buck voltage regulator includes first and second buck converters, first and second low pass filters, and a current balancing loop circuit. The first buck converter includes a first pair of power transistors and a first switch node. The second buck converter includes a second pair of power transistors and a second switch node. The low pass filters are coupled to their respective switch nodes. The current balancing loop circuit receives a filtered output of each filter. The current balancing loop generates a current balancing current signal to control a gain of a first voltage-to-current converter for the second buck converter. The duty cycle of the second buck converter is thereby adjusted, which in turn adjusts a current of the second buck converter to become closer to a current of the first buck converter.

Abstract: An image classification system includes a convolutional neural network, a confidence predictor, and a fusion classifier. The convolutional neural network is configured to assign a plurality of probability values to each pixel of a first image of a scene and a second image of the scene. Each of the probability values corresponds to a different feature that the convolutional neural network is trained to identify. The confidence predictor is configured to assign a confidence value to each pixel of the first image and to each pixel of the second image. The confidence values correspond to a greatest of the probability values generated by the convolutional neural network for each pixel. The fusion classifier is configured to assign, to each pixel of the first image, a feature that corresponds to a higher of the confidence values assigned to the pixel of the first image and the second image.

Abstract: A microelectronic device has bump bond structures on input/output (I/O) pads. The bump bond structures include copper-containing pillars, a barrier layer including cobalt and zinc on the copper-containing pillars, and tin-containing solder on the barrier layer. The barrier layer includes 0.1 weight percent to 50 weight percent cobalt and an amount of zinc equivalent to a layer of pure zinc 0.05 microns to 0.5 microns thick. A lead frame has a copper-containing member with a similar barrier layer in an area for a solder joint. Methods of forming the microelectronic device are disclosed.

Abstract: Systems and methods for a Dual Window Watchdog Timer (DWWDT) are described. In some embodiments, a method may include running a first counter in a first clock domain and a second counter in a second clock domain; generating an interrupt to a controller during a window open period, wherein the window open period begins in response to the first counter having reached a predetermined threshold; and at least one of: restarting the first counter if the controller restarts the second counter in response to the interrupt before the window open period ends; or issuing a system reset if the controller does not restart the second counter in response to the interrupt before the window open period ends.