Abstract: Methods, systems, and apparatus to facilitate high side control of a switching power converter are disclosed. An example apparatus includes a latch including a first node coupled to a first source of a first switch and an output coupled to a first gate of the first switch; a first diode coupled to the first node and a second node; a second diode coupled to the second node and ground; a second switch coupled to a voltage source and the second node; and a third switch including a third gate coupled to the second switch, a third source coupled to the second node, and a third drain coupled to the latch.

Abstract: An electronic device includes a semiconductor substrate having a plurality of trenches formed therein. Each trench includes a sidewall having a doped region, a sidewall liner, and a filler material. The substrate has a slip density of less than 5 cm?2. The low slip density is achieved by a novel annealing protocol performed after implanting the dopant in the sidewall to repair damage and/or stress caused by the implant process.

Abstract: A circuit includes a first common mode amplifier including a first input, a second input, and a first output. The first common mode amplifier comprises a first plurality of self-based differential amplifiers. The circuit also includes a second common mode amplifier including a third input, a fourth input, and a second output, The third input is connected to the second input and the fourth input is connected to the first input. The second common amplifier comprises a second plurality of self-based differential amplifiers. The circuit further includes a first gain amplifier including a fifth input and a sixth input and a second gain amplifier including a seventh input and an eighth input. The first output is connected to the fifth and eight inputs and the second output is connected to the sixth and seventh inputs.

Abstract: In some embodiments, a computer-readable medium stores executable code, which, when executed by a processor, causes the processor to: capture an image of a finder pattern using a camera; locate a predetermined point within the finder pattern; use the predetermined point to identify multiple boundary points on a perimeter associated with the finder pattern; identify fitted boundary lines based on the multiple boundary points; and locate feature points using the fitted boundary lines.

Abstract: A packaged multichip isolation device includes leadframe including a first and second die pad, with a first and second lead extending outside a molded body having a downward extending lead bend near their outer ends. A first integrated circuit (IC) die on the first die pad has a first bond pad connected to the first lead that realizes a transmitter or receiver. A second IC die on the second die pad has a second bond pad connected to the second lead that realizes another of the transmitter and receiver. An isolation component is in a signal path of the isolation device including a capacitive isolator, or inductors for transformer isolation on or between the die. A midpoint of the thickness of the die pad is raised above a top level of the leads and in an opposite vertical direction relative to the downward extending bend of the external leads.

Abstract: In a method for fabricating semiconductor devices a leadframe pattern is formed from a flat tape of base metal. A plurality of additional metal layers is plated on the patterned tape of base metal. The surface of the metal layers is roughed. A plurality of sites for assembling semiconductor chips are created. The sites alternate with zones for connecting the leadframe pattern to molding compound runners A selected first set of leadframe areas are selectively planished creating flattened areas offsetting a second set of leadframe areas. A semiconductor chip is attached to each site.

Abstract: An output of a first amplifier is coupled to an input of a first track and hold circuit and an input of a second track and hold circuit. An input of a first summing circuit is also coupled to an output of the first track and hold circuit and an output of the second track and hold circuit. In addition, an input of a second summing circuit is coupled to the output of the first track and hold circuit and the output of the second track and hold circuit. Moreover, an input of a third summing circuit coupled to an output of a modulator and an output of the second summing circuit, and an output of the third summing circuit coupled to an input of the first amplifier.

Abstract: In described examples of a headlamp to project a beam of light from a lens, the headlamp includes: an illumination module to output a light beam to an illumination path; and illumination optics to receive the light beam and to provide illumination to a programmable spatial light modulator. The programmable spatial light modulator is arranged to receive the illumination and to output non-uniform illumination as patterned light to projection optics. The projection optics are arranged to receive the patterned light and to output the patterned light through the lens. At least one of the illumination optics and the projection optics includes an anamorphic lens to shape the light beam.

Abstract: An apparatus and method system and method for increasing performance in a processor or other instruction execution device while minimizing energy consumption. A processor includes a first execution pipeline and a second execution pipeline. The first execution pipeline includes a first decode unit and a first execution control unit coupled to the first decode unit. The first execution control unit is configured to control execution of all instructions executable by the processor. The second execution pipeline includes a second decode unit, and a second execution control unit coupled to the second decode unit. The second execution control unit is configured to control execution of a subset of the instructions executable via the first execution control unit.

Abstract: A method for coding unit partitioning in a video encoder is provided that includes performing intra-prediction on each permitted coding unit (CU) in a CU hierarchy of a largest coding unit (LCU) to determine an intra-prediction coding cost for each permitted CU, storing the intra-prediction coding cost for each intra-predicted CU in memory, and performing inter-prediction, prediction mode selection, and CU partition selection on each permitted CU in the CU hierarchy to determine a CU partitioning for encoding the LCU, wherein the stored intra-prediction coding costs for the CUs are used.

Abstract: The present disclosure describes systems and methods for controlling access to secure debugging and profiling features of a computer system. Some illustrative embodiments include a system that includes a processor, and a memory coupled to the processor (the memory used to store information and an attribute associated with the stored information). At least one bit of the attribute determines a security level, selected from a plurality of security levels, of the stored information associated with the attribute. Asserting at least one other bit of the attribute enables exportation of the stored information from the computer system if the security level of the stored information is higher than at least one other security level of the plurality of security levels.

Abstract: Disclosed examples include isolated load switch driver circuits to drive a load, including an impedance circuit that receives a digital input voltage signal from a signal source, and selectively allows a current signal to flow from the signal source to charge a buffer capacitor. An impedance control circuit controls the impedance circuit to limit the current signal in response to the buffer capacitor reaching a first threshold voltage, and an output circuit provides an output isolated from the digital input voltage signal to switch the load. A signaling circuit selectively enables the output circuit to draw power from the buffer capacitor in response to the voltage of the buffer capacitor reaching the first threshold voltage.

Abstract: A self-powered electronic system comprises a first chip (401) of single-crystalline semiconductor embedded in a second chip (302) of single-crystalline semiconductor shaped as a container bordered by ridges. The assembled chips are nested and form an electronic device assembled, in turn, in a slab of weakly p-doped low-grade silicon shaped as a container (330) bordered by ridges (331). The flat side (335) of the slab includes a heavily n-doped region (314) forming a pn-junction (315) with the p-type bulk. A metal-filled deep silicon via (350) through the p-type ridge (331) connects the n-region with the terminal (322) on the ridge surface as cathode of the photovoltaic cell with the p-region as anode. The voltage across the pn-junction serves as power source of the device.

Abstract: A process is disclosed of forming metal replacement gates for PMOS transistors with oxygen in the metal gates such that the PMOS gates have effective work functions above 4.85. Metal work function layers in the PMOS gates are oxidized at low temperature to increase their effective work functions to the desired PMOS range. Hydrogen may also be incorporated at an interface between the metal gates and underlying gate dielectrics. Materials for the metal work function layers and processes for the low temperature oxidation are disclosed.

Abstract: A digital-to-analog converter system has digital-to-analog converters, a common output, and a digital controller for transmitting first codes to one of the converters at a radio-frequency digital rate, and for transmitting second codes to another one of the converters at the same rate. The digital controller includes a timing system for operating each converter at the digital rate in a return-to-zero configuration, such that a signal from the first converter is transmitted to the common output while the second converter is reset, and vice versa. The digital-to-analog converter system can generate a radio-frequency analog signal having signals in first and second Nyquist zones simultaneously.

Abstract: An operational amplifier includes an input stage configured to receive a first input voltage and a second input voltage and a slew boost circuit coupled to the input stage and configured to selectively increase current through the input stage. The operational amplifier also includes an output stage coupled to the input stage and configured to generate an output voltage, and a slew boost disable circuit configured to assert a control signal to the slew boost circuit to disable the slew boost circuit. The slew boost circuit is disabled when both: the first input voltage being more than a first threshold voltage different from the second input voltage and the output voltage failing to change by more than a second threshold rate.

Abstract: A microelectronic device includes a metal layer on a first dielectric layer. An etch stop layer is disposed over the metal layer and on the dielectric layer directly adjacent to the metal layer. The etch stop layer includes a metal oxide, and is less than 10 nanometers thick. A second dielectric layer is disposed over the etch stop layer. The second dielectric layer is removed from an etched region which extends down to the etch stop layer. The etched region extends at least partially over the metal layer. In one version of the microelectronic device, the etch stop layer may extend over the metal layer in the etched region. In another version, the etch stop layer may be removed in the etched region. The microelectronic device is formed by etching the second dielectric layer using a plasma etch process, stopping on the etch stop layer.

Abstract: Channel switchover power multiplexer circuits, and methods of operating the same are disclosed. An example power multiplexer a first transistor coupled to a first input, a second transistor coupled to the first transistor to couple a first voltage at the first input to an output, a third transistor coupled to a second input, a fourth transistor coupled to the third transistor to couple a second voltage at the second input to the output, a diode amplifier to provide a third voltage to a gate of the first transistor to block a reverse current, and a soft-start amplifier to provide a fourth voltage to a gate of the fourth transistor to turn on (with adjustable VOUT ramp rate) the fourth transistor with a constant ramp rate.

Abstract: A physical layer integrated circuit (PHY), including an accessory charger adapter (ACA) bridge circuit to communicate with an ACA via a universal serial bus (USB) cable having at least an ID pin and a VBUS pin. The PHY is also to communicate with an ACA-agnostic USB controller configured to act as an A-device or as a B-device. The ACA comprises a USB accessory port. The ACA bridge circuit comprises detection and control logic configured to detect, based on a resistance sensed on the ID pin, that a B-device is connected to the USB accessory port of the ACA and, as a result of such a detection, generate a signal to the USB controller that causes the USB controller to act as an A-device and ignore a VBUS drive signal from the USB controller that, if not ignored, would cause the PHY to drive the VBUS pin.

Abstract: A method includes: generating, via a testing signal source, a test transmission signal; receiving the test transmission signal at an input port of a socket device having the input port, an input coupler, a divider, a combiner, an output coupler and an output port; providing, via the input coupler, an input signal based on the test transmission signal; providing, via the divider, portions of the input signal to each of respective inputs of m receivers of a transceiver having n transmitters and the m receivers; combining, via the combiner, signals provided at the respective outputs of the n transmitters into a combined output signal; providing a coupled output signal to the input coupler; providing a measured output signal to the output port; providing, via the output port, the measured output signal to a receiving signal measuring device; and testing, via the receiving signal measuring device, the measured output signal.