Patents Assigned to Texas Instruments
  • Electronic device and method for tracking energy consumption
    Patent number: 10324116
    Abstract: The invention relates to an apparatus and method for tracking energy consumption. An energy tracking system comprises at least one switching element, at least one inductor and a control block to keep the output voltage at a pre-selected level. The switching elements are configured to apply the source of energy to the inductors. The control block compares the output voltage of the energy tracking system to a reference value and controls the switching of the switched elements in order to transfer energy for the primary voltage into a secondary voltage at the output of the energy tracking system. The electronic device further comprises an ON-time and OFF-time generator and an accumulator wherein the control block is coupled to receive a signal from the ON-time and OFF-time generator and generates switching signals for the at least one switching element in the form of ON-time pulses with a constant ON-time.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: June 18, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Horst Diewald, Johann Zipperer, Peter Weber, Anton Brauchle
  • Circuit reliability improvement by detecting and mitigating high voltage transient event at supply
    Patent number: 10326268
    Abstract: A circuit reliability system with a first voltage supply for outputting a first voltage and a second voltage supply for outputting a second voltage. The system also includes: (i) at least one node for providing a potential in response to the first voltage and the second voltage; (ii) monitoring circuitry for detecting the first voltage exceeding a threshold; and (iii) disabling circuitry, for disabling the second voltage supply in response to the monitoring circuitry detecting the first voltage exceeding a threshold.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: June 18, 2019
    Assignee: Texas Instruments Incorporated
    Inventors: Eung J. Kim, Md. Abidur Rahman, Sualp Aras
  • Level shifter circuit generating bipolar clock signals
    Patent number: 10326451
    Abstract: In some examples, a level shifter circuit comprises: a first transistor pair cascoded at a first input node; a second transistor pair cascoded at a second input node, wherein the first and transistor pairs couple at a first node, a second node, a third node, and a fourth node; a third transistor pair coupled to the first transistor pair at the first and the third nodes, wherein the third transistor pair is configured to generate a first bipolar clock signal; a fourth transistor pair coupled to the second transistor pair at the second and the fourth nodes, wherein the fourth transistor pair is configured to generate a second bipolar clock signal; and a clock generation circuit coupled to the first node, the second node, the third node, and the fourth node.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: June 18, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Biraja Prasad Dash, Ravinthiran Balasingam, Dimitar Trifonov
  • METHODS FOR TRANSISTOR EPITAXIAL STACK FABRICATION
    Publication number: 20190181240
    Abstract: Disclosed examples provide methods for fabricating an epitaxial layer stack for a gallium nitride transistor in an integrated circuit, including forming an aluminum nitride layer (AlN) on a substrate with a predetermined resistivity in a processing chamber, forming an aluminum gallium nitride layer (AlGaN) on the AlN layer in the processing chamber, forming a surface layer on the AlGaN layer in the processing chamber, and controlling the processing chamber temperature after forming the surface layer to cool the substrate and the formed layers at a controlled rate to control wafer bow.
    Type: Application
    Filed: December 13, 2017
    Publication date: June 13, 2019
    Applicant: Texas Instruments Incorporated
    Inventors: Qhalid Fareed, Asad Mahmood Haider
  • BACK BALLASTED VERTICAL NPN TRANSISTOR
    Publication number: 20190181134
    Abstract: Disclosed examples provide fabrications methods and integrated circuits with back ballasted NPN bipolar transistors which include an n-type emitter in a P doped region, a p-type base with a first side facing the emitter, and an n-type collector laterally spaced from a second side of the base, where the collector includes a first side facing the second side of the base, an opposite second side, a silicided first collector portion and a silicide blocked second collector portion covered with a non-conductive dielectric that extends laterally between the first collector portion and the second side of the collector to provide back side ballasting for lateral breakdown and low current conduction via a deep N doped region while the vertical NPN turns on at a high voltage.
    Type: Application
    Filed: December 12, 2017
    Publication date: June 13, 2019
    Applicant: Texas Instruments Incorporated
    Inventors: Akram Ali Salman, Guruvayurappan Mathur, Ryo Tsukahara
  • Integrated transistor and protection diode and fabrication method
    Patent number: 10319712
    Abstract: Disclosed examples provide integrated circuits including a source down transistor with a gate, a body region, an n-type source region, an n-type drain region, a p-type body contact region below the n-type source region which extends to a first depth, along with a protection diode which includes an n-type cathode region, and a p-type anode region below the n-type cathode region, where the breakdown voltage of the protection diode is defined by adjusting the relative doping concentrations and/or the vertical locations of the p-type anode region with respect to the n-type cathode region.
    Type: Grant
    Filed: October 11, 2017
    Date of Patent: June 11, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Haian Lin, Frank Baiocchi
  • Memory compression operable for non-contiguous write/read addresses
    Patent number: 10320412
    Abstract: Disclosed embodiments include a system having a first memory, a second memory, circuitry that reads data quantities from the first memory along a first orientation, a compression engine that compresses each of the read data quantities to produce corresponding compressed data quantities, and circuitry that writes the compressed data quantities to the second memory along a second orientation which differs from the first orientation. The read data quantities have a first bit width and the compressed data quantities have a second bit width that is less than the first bit width.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: June 11, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sundarrajan Rangachari, Desmond Pravin Martin Fernandes, Rakesh Channabasappa Yaraduyathinahalli
  • Detection of plunger movement in DC solenoids through current sense technique
    Patent number: 10317453
    Abstract: An apparatus and method of detecting movement of a plunger of the solenoid includes detecting a peak (IPEAK) in a current signal applied to a coil of the solenoid. A predetermined threshold is added to the current signal applied to the coil of the solenoid to generate a level shifted signal. The level shifted signal and the peak signal are compared to detect movement of a plunger of the solenoid.
    Type: Grant
    Filed: June 13, 2018
    Date of Patent: June 11, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Navaneeth Kumar Narayanasamy, Manu Balakrishnan
  • Headlamp with digital micromirror device and static reflector
    Patent number: 10317032
    Abstract: A headlamp includes a digital micromirror device (DMD) reflector, a light source, and projection optics. The DMD reflector includes a DMD and a static reflector disposed on a plurality of sides of the DMD. The light source is disposed to illuminate the DMD reflector. The projection optics are configured to project light reflected by the DMD and light reflected by the static reflector via a same lens system.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: June 11, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Vikrant R. Bhakta, Jeff Farris, Stephen A. Shaw
  • Spike safe floating current and voltage source
    Patent number: 10317456
    Abstract: Spike safe floating current and voltage source (VI) containing a forced voltage amplifier in series with a selectable resistor. A method of providing a VI with forced current testing mode using a forced voltage amplifier in series with a selectable resistor. A method of providing a VI with forced voltage testing mode using a forced voltage amplifier in series with a selectable resistor. A method of measuring the on resistance of a device under test using a VI with a forced voltage amplifier in series with a selectable resistor. A method of measuring the breakdown of an input/output junction of a device under test using a VI with a forced voltage amplifier in series with a selectable resistor.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: June 11, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Ramana Tadepalli
  • Method and apparatus for real-time SAO parameter estimation
    Patent number: 10321135
    Abstract: The disclosure provides a sample adaptive offset (SAO) encoder. The SAO encoder includes a statistics collection (SC) block and a rate distortion optimization (RDO) block coupled to the SC block. The SC block receives a set of deblocked pixels and a set of original pixels. The SC block categorizes each deblocked pixel of the set of deblocked pixels in at least one of a plurality of band and edge categories. The SC block estimates an error in each category as difference between a deblocked pixel of the set of deblocked pixels and corresponding original pixel of the set of original pixels. The RDO block determines a set of candidate offsets associated with each category and selects a candidate offset with a minimum RD cost. The minimum RD cost is used by a SAO type block and a decision block to generate final offsets for the SAO encoder.
    Type: Grant
    Filed: May 3, 2018
    Date of Patent: June 11, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Hrushikesh Tukaram Garud, Mihir Narendra Mody, Soyeb Nagori
  • Attenuating common mode noise current in current mirror circuits
    Patent number: 10317925
    Abstract: At least some embodiments are directed to a system comprising a capacitor coupled to a voltage supply rail and configured to carry a capacitor current that comprises first and second parts. The capacitor current is an alternating current (AC). A first current mirror component may couple to the capacitor and to the voltage supply rail and is configured to carry the first part of the capacitor current. A second current mirror component couples to the voltage supply rail and is configured to carry the second part of the capacitor current. The second part of the capacitor current is proportionally related to the first part of the capacitor current. A circuit couples to the second current mirror component. The capacitor and the first and second current mirror components are configured to attenuate a common mode noise current flowing to the circuit.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: June 11, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Nitin Agarwal, Rajavelu Thinakaran, Sumit Dubey
  • Reducing context coded and bypass coded bins to improve context adaptive binary arithmetic coding (CABAC) throughput
    Patent number: 10321131
    Abstract: Techniques for context-adaptive binary arithmetic coding (CABAC) coding with a reduced number of context coded and/or bypass coded bins are provided. Rather than using only truncated unary binarization for the syntax element representing the delta quantization parameter and context coding all of the resulting bins as in the prior art, a different binarization is used and only part of the resulting bins are context coded, thus reducing the worst case number of context coded bins for this syntax element. Further, binarization techniques for the syntax element representing the remaining actual value of a transform coefficient are provided that restrict the maximum codeword length of this syntax element to 32 bits or less, thus reducing the number of bypass coded bins for this syntax element over the prior art.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: June 11, 2019
    Assignee: Texas Instruments Incorporated
    Inventors: Vivienne Sze, Madhukar Budagavi
  • Inductive structures with improved common mode transient immunity
    Patent number: 10320448
    Abstract: In described examples, an inductive structure includes first and second inductive coils to conduct respective first and second common mode currents induced by a common mode transient between: a first ground coupled to a connection between the first and second inductive coils; and a galvanically isolated second ground.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: June 11, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Rajaram Subramonian, Gianpaolo Lisi, Swaminathan Sankaran, Bradley Allen Kramer, Gerard Socci
  • High definition VP8 decoder
    Patent number: 10321163
    Abstract: A VP8 video decoder is implemented by partitioning the required functions across multiple sub systems, with an optimal mapping to existing functional blocks. Key optimizations include the reuse of hardware designed for prior generation VP6 and VP7 decoders. In order to reduce implementation complexity, cost and power consumption, a non-exact, approximate deblocking loop filter is implemented.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: June 11, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Mihir Narendra Mody, Chaitanya S Ghone, Joseph Meehan
  • High speed level shifter for high voltage applications
    Patent number: 10319362
    Abstract: The disclosure provides a level shifter. The level shifter includes a first logic block that receives an input signal and generates a primary pulsed input. A first transistor is coupled to the first logic block and a first node. A gate terminal of the first transistor receives the primary pulsed input. A latch is coupled to the first node and a second node. A second logic block receives the input signal and generates a secondary pulsed input. A second transistor is coupled between the second logic block and the second node. A gate terminal of the second transistor receives the secondary pulsed input.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: June 11, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ravikumar Pattipaka, Raja Sekhar Kanakamedala, Aravind Miriyala, Sandeep Kesrimal Oswal
  • Method of determining a direction of rotation and valid transitions of quadrature pulses
    Patent number: 10320594
    Abstract: A method of determining a direction of rotation of a shaft is disclosed, as well as an integrated circuit chip that uses the disclosed method. The method includes receiving a first binary signal and a second binary signal from a transducer attached to the shaft, with the first and second binary signals being in quadrature. A present quadrant identification number, QIDPRESENT, is determined as a two-digit binary number by left-shifting a value of the first signal and adding a value of the second signal. After a sampling interval has elapsed, the method sets a past quadrant identification number, QIDPAST, to the value of said QIDPRESENT, determines a new value of QIDPRESENT and calculates a value of a transition code using an equation that operates on QIDPRESENT and QIDPAST. The method uses the transition code to determine a direction of rotation of the shaft.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: June 11, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Richard Mark Poley
  • Method of forming a semiconductor device
    Patent number: 10319899
    Abstract: A microelectronic device containing a piezoelectric thin film element is formed by oxidizing a top surface of a piezoelectric layer with an oxygen plasma, and subsequently forming an etch mask containing photoresist on the oxidized top surface. The etch mask is conditioned with an oven bake followed by a UV bake. The piezoelectric layer is etched using a three step process: a first step includes a wet etch of an aqueous solution of about 5% NH4F, about 1.2% HF, and about 18% HCl, maintaining a ratio of the HCl to the HF of about 15.0, which removes a majority of the piezoelectric layer. A second step includes an agitated rinse. A third step includes a short etch in the aqueous solution of NH4F, HF, and HCl.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: June 11, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Neng Jiang, Xin Li, Joel Soman, Thomas Warren Lassiter, Mary Alyssa Drummond Roby, YungShan Chang
  • Structures to avoid floating resurf layer in high voltage lateral devices
    Patent number: 10319809
    Abstract: A semiconductor device contains an LDNMOS transistor with a lateral n-type drain drift region and a p-type RESURF region over the drain drift region. The RESURF region extends to a top surface of a substrate of the semiconductor device. The semiconductor device includes a shunt which is electrically coupled between the RESURF region and a low voltage node of the LDNMOS transistor. The shunt may be a p-type implanted layer in the substrate between the RESURF layer and a body of the LDNMOS transistor, and may be implanted concurrently with the RESURF layer. The shunt may be through an opening in the drain drift region from the RESURF layer to the substrate under the drain drift region. The shunt may be include metal interconnect elements including contacts and metal interconnect lines.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: June 11, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Yongxi Zhang, Philip L. Hower, John Lin, Guru Mathur, Scott G. Balster, Constantin Bulucea, Zachary K. Lee, Sameer P. Pendharkar
  • Pattern based estimation of errors in ADC
    Patent number: 10320405
    Abstract: In described examples, an analog to digital converter (ADC) includes a flash ADC. The flash ADC generates a flash output in response to an input signal, and an error correction block generates a known pattern. A selector block is coupled to the flash ADC and the error correction block, and generates a plurality of selected signals in response to the flash output and the known pattern. A digital to analog converter (DAC) is coupled to the selector block, and generates a coarse analog signal in response to the plurality of selected signals. A residue amplifier is coupled to the DAC, and generates a residual analog signal in response to the coarse analog signal, the input signal and an analog PRBS (pseudo random binary sequence) signal. A residual ADC generates a residual code in response to the residual analog signal.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: June 11, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Srinivas Kumar Reddy Naru, Visvesvaraya Pentakota Appala, Shagun Dusad, Neeraj Shrivastava, Viswanathan Nagarajan, Ani Xavier, Rishi Soundararajan, Sai Aditya Nurani, Roswald Francis