Abstract: Disclosed embodiments relate to processing of gestures to cause computation of measurements of a line using a touch screen. A system includes a processor, a touch screen coupled to the processor, a gesture module coupled to the processor for executing a gesturing method. The method includes determining a gesture shape and whether the gesture shape selects a first line segment by intersecting the first line segment. When the gesture shape selects a first line segment, it is then determined whether the gesture shape also selects an additional line segment different from the first line segment. When an additional line segment is not selected, the method calculates the length measurement from the beginning point of the segment to the end point of the selected first line segment. The method further displays the length measurement on a display.

Abstract: Described examples include an integrated circuit including a receive portion to receive an encoded transmission on a line. The receive portion has: a wake mode in which the receiver is capable of receiving the encoded transmission; and a sleep mode in which the receiver is not capable of receiving the encoded transmission. A wakeup controller monitors the line for a wakeup signal and provides a signal to the receive portion to cause the receive portion to enter the wake mode when the wakeup controller receives the wakeup signal.

Abstract: An address and command port interface selectively enables JTAG TAP domain operations and Trace domain operations within an IC. The port carries TMS and TDI input and TDO output on a single pin and receives a clock signal on a separate pin. The addressable two pin interface loads and updates instructions and data to the TAP domain within the IC. The instruction or data update operations in multiple ICs occur simultaneously. A process transmits data from an addressed target device to a controller using data frames, each data frame comprising a header bit and data bits. The logic level of the header bit is used to start, continue, and stop the data transmission to the controller. A data and clock signal interface between a controller and multiple target devices provides for each target device to be individually addressed and commanded to perform a JTAG or Trace operation.

Abstract: A class-D amplifier includes an output driver, a pulse width modulator, an integrator, and duty cycle control circuitry. The output driver is configured to drive a loudspeaker. The pulse width modulator is coupled to the output driver. The integrator is coupled to the pulse width modulator. The duty cycle control circuitry is coupled to the integrator. The duty cycle control circuitry is configured to monitor amplitude of output signal of the integrator, and change an average duty cycle of signal at an output of the output driver as a function of the amplitude.

Abstract: A system and method for minimizing or preventing interference between wireless networks is disclosed. A network hub broadcasts a beacon signal within repeating beacon periods. The position of the beacon signal shifts within each beacon period based upon a predetermined pseudo-random sequence. The beacon signal includes data identifying the current beacon shift sequence and the current phase of the sequence. Neighboring hubs independently or jointly determine and broadcast their own beacon shift sequences and phases for their respective networks from a predetermined list. Nodes connected with the network hubs are assigned allocation intervals having a start time that is set relative to the beacon signal. The start time and duration of the allocation interval wraps around the beacon period if the allocation-interval would otherwise start or continue in a next beacon period.

Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements for the nested loops. A steam head register stores data elements next to be supplied to functional units for use as operands. A stream template register independently specifies a linear address or a circular address mode for each of the nested loops.

Abstract: A predication method for vector processors that minimizes the use of embedded predicate fields in most instructions by using separate condition code extensions. Dedicated predicate registers provide fine grain predication of vector instructions where each bit of a predicate register controls 8 bit of the vector data.

Abstract: A semiconductor device includes a NMOS transistor with a back gate connection and a source region disposed on opposite sides of the back gate connection. The source region and back gate connection are laterally isolated by an STI oxide layer which surrounds the back gate connection. The NMOS transistor has a gate having a closed loop configuration, extending partway over a LOCOS oxide layer which surrounds, and is laterally separated from, the STI oxide layer. A lightly-doped drain layer is disposed on opposite sides of the NMOS transistor, extending under the LOCOS oxide layer to a body region of the NMOS transistor. The LOCOS oxide layer is thinner than the STI oxide layer, so that the portion of the gate over the LOCOS oxide layer provides a field plate functionality. The NMOS transistor may optionally be surrounded by an isolation structure which extends under the NMOS transistor.

Abstract: A rear-stitched view panorama (RSVP) system is provided that includes at least one processor and a memory storing software instructions that, when executed by the least one processor, cause the RSVP system to compute a disparity map for a left center rear image and a right center rear image captured by a stereo camera mounted on a rear of a vehicle, transform a right rear image, a left rear image, a reference center rear image, and the disparity map to a virtual world view, the right rear image and left rear image captured by respective right and left cameras mounted on the vehicle, compute an optimal left seam and an optimal right seam based on the transformed disparity map, and stitch the transformed images based on respective optimal seams to generate a panorama.

Abstract: In described examples, a switch has: a first current handling terminal coupled to a supply source terminal; and a second current handling terminal coupled to an output terminal. A comparator has: a first input coupled to the second current handling terminal; and a second input. A voltage reference source has: a first terminal coupled to the first current handling terminal; and a second terminal coupled to the second input of the comparator. A slew rate detector has an input coupled to the second current handling terminal. A switch controller has: a first input coupled to the comparator output; and a second input coupled to an output of the slew rate detector. The switch controller is coupled to output a signal to cause the switch to open when the comparator detects an over-current condition through the switch while the slew rate detector detects a negative slew rate.

Abstract: A predictive back-emf protection methodology for an electromechanical system, including a signal processor that processes a source signal to provide a modified source signal, a driver that converts the modified source signal to a drive signal, and an electromechanical transducer that generates, from the drive signal, a transducer response, and a back-emf signal coupled back to the driver output. A predictive back-emf generator (such as a routine in the signal processor) is characterized by a back-emf transfer function (linear parameterized model of the electromechanical transducer) for transforming an input signal into a transform back-emf representation of a back-emf signal predicted by the back-emf transfer function as a response of the electromechanical transducer to such input signal. The signal processor processes the source signal based on the transform back-emf representation to generate the modified source signal input to the driver.

Abstract: In some examples, an electrostatic discharge (ESD) device includes a substrate layer, a transition layer positioned on the substrate layer, a plurality of superlattice layers on the transition layer and including at least two doped superlattice layers. The ESD device further includes a plurality of doped contact structures extending from the transition layer to a surface of an outermost layer of the plurality of superlattice layers, where a first of the plurality of doped contact structures comprises an anode and a second of the plurality of doped contact structures comprises a cathode, where the plurality of doped contact structures are to generate a zero capacitance ESD device.

Abstract: Methods, apparatus, systems and articles of manufacture to optimize power consumption and capacity in a multi-mode communication system are disclosed. A utilization factor controller is to estimate power consumption values corresponding to a plurality of first utilization factor and second utilization factor pairs, the first utilization factor corresponding to utilization of the first transceiver that is to communicate using a first protocol, the second utilization factor corresponding to utilization of the second transceiver that is to communicate using a second protocol different form the first protocol, the utilization factor controller to select a first utilization factor and second utilization factor pair based on the estimated power consumption value. A transmission time controller is to calculate first and second transmission times to be used by the first and second transceiver based on the selected first utilization factor and second utilization factor pair.

Abstract: A capacitive sensing system based on projected self-capacitance is suitable for use in printing systems/products to sense paper tray status. In example embodiments, a capacitive sensing system is adapted for sensing the condition/characteristics of paper in the paper tray, such as paper size, stack height and page count and paper dielectric. The capacitive sensing system can be configured with one or more shielded capacitive sensors incorporated into the paper tray, and oriented relative to the paper according to the paper condition/characteristic sensed.

Abstract: A gate control circuit for a tristate output buffer operating in a first voltage domain includes a pull-up circuit coupled between an upper rail and a first gate control signal, a pull-down circuit coupled between a lower rail and a second gate control signal, and a gate isolation switch coupled between the first gate control signal and the second gate control signal. The gate isolation switch includes a first PMOS transistor coupled in parallel with a first NMOS transistor. The first NMOS transistor is controlled by a first enable signal and the first PMOS transistor is controlled by a second enable signal.

Abstract: A battery charger circuit having a regulator controller configured to control the switching transistors of a switching voltage regulator. A power path switch is disposed intermediate an output of the switching voltage regulator and a terminal of a battery to be charged, with the power path switch including at least two transistor segments having common respective drain electrodes, common respective source electrodes and separate respective gate electrodes. A power path switch controller operates to sequentially turn ON the at least two transistor segments of the power path switch, preferably in the order of a decreasing ON resistance.

Abstract: A dual leadframe (100) for semiconductor systems comprising a first leadframe (110) having first metal zones separated by first gaps, the first zones including portions of reduced thickness and joint provisions in selected first locations, and further a second leadframe (120) having second metal zones separated by second gaps, the second zones including portions of reduced thickness and joint provisions (150) in selected second locations matching the first locations. The second leadframe is stacked on top of the first leadframe and the joint provisions of the matching second and first locations linked together. The resulting dual leadframe may further include insulating material (140) filling the first and second gaps and the zone portions of reduced thickness, and has insulating surfaces coplanar with the top and bottom metallic surfaces.

Abstract: An electronic device, that in various embodiments includes a first semiconductor layer comprising a first group III nitride. A second semiconductor layer is located directly on the first semiconductor layer and comprises a second different group III nitride. A cap layer comprising the first group III nitride is located directly on the second semiconductor layer. A dielectric layer is located over the cap layer and directly contacts the second semiconductor layer through an opening in the cap layer.

Abstract: A gate driver includes a drive signal input terminal, a drive signal output terminal, a gate drive circuit, and a serial communication interface. The drive signal input terminal is configured to receive a gate drive signal. The gate drive circuit is coupled to the drive signal input terminal and the drive signal output terminal. The gate drive circuit is configured to provide the gate drive signal to the drive signal output terminal. The serial communication interface is coupled to the drive signal input terminal.

Abstract: An integrated circuit package includes a first die that has a microelectromechanical system (MEMS) resonator coupled to a coil. A second die includes a coil fabricated on a top surface of the second die, and an electronic circuit with tank circuit terminals fabricated on the second die and coupled to the second coil. The second die is positioned adjacent the first die such that the first coil is operable to electromagnetically couple to the second coil.