Abstract: An apparatus includes an output transistor device configured to control an output voltage of an output node in response to a control signal and an input voltage. A current sensor is configured to sense an output current supplied from the output node. A feedback converter is configured to convert the sensed output current to a feedback signal that tracks the output voltage of the output node. The feedback converter is further configured to set a clamping threshold. A gate control circuit is configured to generate the control signal in response to the feedback signal. The gate control circuit is configured to clamp the output voltage of the output node via the control signal based on the clamping threshold.

Abstract: This invention is a bus communication protocol. A master device stores bus credits. The master device may transmit a bus transaction only if it holds sufficient number and type of bus credits. Upon transmission, the master device decrements the number of stored bus credits. The bus credits correspond to resources on a slave device for receiving bus transactions. The slave device must receive the bus transaction if accompanied by the proper credits. The slave device services the transaction. The slave device then transmits a credit return. The master device adds the corresponding number and types of credits to the stored amount. The slave device is ready to accept another bus transaction and the master device is re-enabled to initiate the bus transaction. In many types of interactions a bus agent may act as both master and slave depending upon the state of the process.

Abstract: A circuit comprises: a pass transistor; a first transistor comprising a gate coupled to the gate of the pass transistor, a source coupled to the source of the pass transistor, and a drain; a second transistor comprising a gate coupled to the gate of the pass transistor, a source coupled to the source of the pass transistor, and a drain; a first current mirror coupled to the drain of the first transistor; a second current mirror coupled to the drain of the second transistor, and coupled to the first current mirror; a feedback voltage circuit coupled to the drain of the pass transistor; an error amplifier comprising a first input port coupled to the feedback voltage circuit, and an output port coupled to the gate of the pass transistor; and a capacitor coupled to the second current mirror and to the first input port of the error amplifier.

Abstract: An apparatus for enhancing the thermal performance of semiconductor packages effectively. The concept of this invention is to provide silicon nanowires on the backside of an integrated circuit die to directly attach the die to the substrate, thereby improving the interface between die and substrate, and thus enhancing thermal performance and enhancing reliability by improving adhesion.

Abstract: A programmable gain amplifier includes an operational amplifier and a resistor network coupled to the output node of the operational amplifier. The resistor network includes a first plurality of resistors coupled in series between the output node and a first network node. A second plurality of resistors is coupled in series between the first network node and a second network node. A unit resistor is coupled in parallel with the second plurality of resistors between the first and second resistor network nodes and a third plurality of resistors is coupled in parallel between the second resistor network node and a reference voltage. Each resistor of the second and third pluralities of resistors comprises a unit resistor. The third plurality of resistors contains N resistors and the second plurality of resistors contains (N?1) resistors.

Abstract: Methods and apparatus for operating a communication system comprising three or more communication transceivers. In illustrative embodiments, multiple different cyclic redundancy check (CRC) generation schemes are maintained. Each CRC generation scheme corresponds to a unique CRC residual value. A CRC value generated using one of the CRC generation schemes is placed in a data packet to be transmitted. The chosen CRC generation scheme reflects which one or more transceivers are intended recipients of the data packet. When a data packet is received by a transceiver, a CRC residual value is calculated based on the CRC value contained in the received data packet. The calculated CRC residual value is compared against a list of one or more valid CRC residual values for that particular transceiver. If the calculated CRC value matches one of the listed valid CRC residual values, the data packet is accepted, otherwise it is rejected.

Abstract: A method of channel access for a radio device in an asynchronous channel hopping wireless network includes a channel hopping coordinator first radio device transmitting its receive (Rx) channel hopping sequence to a fixed or semi-channel hopping sleepy radio device. The sleepy radio device tracks the first radio device's Rx channel using the channel hopping sequence and transmits a poll frame exclusive of a unicast schedule information element (US-IE) on the first radio device's current Rx channel to the first radio device. The sleepy radio device moves to an updated Rx channel that is a function of the current Rx channel. The first radio device receives the poll frame and then computes the updated Rx channel as the function of the current Rx channel. After the computing, the first radio device transmits a data frame to the sleepy radio device on the updated Rx channel.

Abstract: A first-order sigma-delta analog-to-digital converter includes an input terminal, an integrator circuit, a comparator, and control circuitry. The input terminal is configured to receive a unipolar input signal to be digitized. The integrator circuit is coupled to the input terminal. The comparator is coupled to an output of the integrator circuit. The control circuitry is coupled to the integrator circuit and the comparator. The control circuitry is configured to equalize time that an output signal generated by the integrator circuit is greater than zero and time that the output signal generated by the integrator circuit is less than zero during digitization of the unipolar input signal.

Abstract: An apparatus includes a preamplifier stage to receive a power supply voltage and generate an output based upon an input. In particular, the preamplifier stage includes a biasing device coupled between the output and a ground node to bias a DC voltage level of the output independently of the power supply voltage. The preamplifier stage also includes a complementary circuit to receive the input and generate the output. The complementary circuit reuses a current through the preamplifier stage to provide an increased transconductance of the preamplifier stage for a given current level.

Abstract: Disclosed examples include semiconductor devices and fabrication methods to fabricate semiconductor wafers and integrated circuits, including forming a first epitaxial semiconductor layer of a first conductivity type on a first side of a semiconductor substrate of the first conductivity type, forming a nitride or oxide protection layer on a top side of the first epitaxial semiconductor layer, forming a second epitaxial semiconductor layer of the first conductivity type on the second side of the semiconductor substrate, and removing the protection layer from the first epitaxial semiconductor layer. The wafer can be used to fabricate an integrated circuit by forming a plurality of transistors at least partially on the first epitaxial semiconductor layer.

Abstract: A receiver module includes a clock recovery circuit and a decision feedback equalizer (DFE) circuit. The DFE circuit includes a data feedback loop configured to sample an input data stream combined with equalization values based on a first clock signal. The DFE circuit also includes an edge feedback loop configured to sample the input data stream combined with equalization values based on a second clock signal. The clock recovery circuit is configured to determine a phase error between a receiver clock signal and a target clock signal based on output samples from the data feedback loop and the edge feedback loop.

Abstract: An FMCW radar is used to detect live objects by processing the matched, filtered radar return on a frame by frame basis. An FFT cross correlation coefficient is computed, followed by computing a modified geometric mean of the absolute value of the cross correlation coefficients. The modified geometric mean is then compared to a preset threshold to determine whether the object is moving or is stationary.

Abstract: One example includes a test system that includes a printed circuit board and a switching interposer board. The switching interposer board is comprised of a probe point, a first bus, a second bus, and a set of switches. Each switch includes a first terminal, a second terminal, and a third terminal, the first terminal being coupled to a respective pin of an integrated circuit device, the second terminal being coupled to the first bus, and the third terminal being coupled to the second bus. Each of the set of switches have a first state that selectively couples a pair of the pins of the integrated circuit device to each other through the first bus during a short test, and a second state that selectively couples at least one of the pins of the integrated circuit device to the probe point through the second bus during a voltage level spike test.

Abstract: One example includes an interleaved resonant converter circuit. The circuit includes a plurality of resonant converter circuits that are each coupled to an output node and are configured to collectively generate an output voltage on the output node in response to a respective plurality of sets of switching signals at each of a respective plurality of phases. The circuit also includes a switching controller configured to generate each of the plurality of sets of switching signals having a variable duty-cycle relative to each other at each of the plurality of phases.

Abstract: In some examples, a method includes etching a substrate to form a trench, wherein the trench includes sidewalls. The method further includes forming a first isolation region in the trench by growing a first layer of a first thickness on the sidewalls using a dry oxidation technique and depositing a second layer to fill a portion of the trench, the second layer contacting the first layer. The method further includes etching third and fourth layers atop the substrate to expose a first portion of the substrate. The method further includes growing a second isolation region in the substrate through the first portion by using a dry-wet-dry oxidation technique.

Abstract: A digital system has a dielectric core waveguide that has a longitudinal dielectric core member. The core member has a body portion and a transition region, with a cladding surrounding the dielectric core member. The body portion of the core member has a first dielectric constant. The transition region of the core member has a graduated dielectric constant value that gradually changes from the first dielectric constant value adjacent the body portion to a third dielectric constant.

Abstract: A microelectronic device includes a gated graphene component over a semiconductor material. The gated graphene component includes a graphitic layer having at least one layer of graphene. The graphitic layer has a channel region, a first connection and a second connection make electrical connections to the graphitic layer adjacent to the channel region. The graphitic layer is isolated from the semiconductor material. A backgate region having a first conductivity type is disposed in the semiconductor material under the channel region. A first contact field region and a second contact field region are disposed in the semiconductor material under the first connection and the second connection, respectively. At least one of the first contact field region and the second contact field region has a second, opposite, conductivity type. A method of forming the gated graphene component in the microelectronic device with a transistor is disclosed.

Abstract: A methodology for capturing analog information, such as from an analog sensor, including converting the analog information to a train of pulses, representing the analog information as the number of pulses in the pulse train. This pulse count data can be communicated to a processor configured to count the pulses in the pulse train, and convert this pulse count data into digital data corresponding to the analog information. An example embodiment uses a DAC/comparator to convert the analog information (such as a sensor reading) into a pulse train derived from a DAC count (such as can be generated by a DAC counter from an input DAC clock) that is compared with an analog magnitude (analog information), such that the DAC count, which can be represented by a number of DAC clock pulses, provides the pulse train (pulse count data) that corresponds to the analog information.

Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements for the nested loops. A steam head register stores data elements next to be supplied to functional units for use as operands. A stream template register specifies a circular address mode for the loop, first and second block size numbers and a circular address block size selection. For a first circular address block size selection the block size corresponds to the first block size number. For a first circular address block size selection the block size corresponds to the first block size number. For a second circular address block size selection the block size corresponds to a sum of the first block size number and the second block size number.

Abstract: An integrated circuit is formed on a substrate containing a semiconductor material having a first conductivity type. A deep well having a second, opposite, conductivity type is formed in the semiconductor material of the first conductivity type. A deep isolation trench is formed in the substrate through the deep well so as separate an unused portion of the deep well from a functional portion of the deep well. The functional portion of the deep well contains an active circuit element of the integrated circuit. The separated portion of the deep well does not contain an active circuit element. A contact region having the second conductivity type and a higher average doping density than the deep well is formed in the separated portion of the deep well. The contact region is connected to a voltage terminal of the integrated circuit.