Abstract: This invention addresses implements a range of interesting technologies into a single block. Each DSP CPU has a streaming engine. The streaming engines include: a SE to L2 interface that can request 512 bits/cycle from L2; a loose binding between SE and L2 interface, to allow a single stream to peak at 1024 bits/cycle; one-way coherence where the SE sees all earlier writes cached in system, but not writes that occur after stream opens; full protection against single-bit data errors within its internal storage via single-bit parity with semi-automatic restart on parity error.

Abstract: A method of probing wafers includes providing a processor running a parametric test program generator algorithm which execute steps including reading a stored first probe program including a first test sequence (TS1) having a first tests configured for probing at least a first circuit element (FCE) in a first scribe line module. TS1 includes (i) electrical pinning and geometrical data and (ii) first Variable Group data specific for the FCE including first test parameters having at least first forcing conditions. The (ii) is modified with modified second variable group data specific to a second circuit element (SCE) in a second scribe line module. The modified second Variable Group data includes modified second test parameters having second forcing conditions. (i) of TS1 is merged with the modified second Variable Group data to generate code for a second test sequence of a second probe program that is configured for probing the SCE.

Abstract: A circuit for sensing current in a capacitive network. A first capacitor carries a first current. A second capacitor is connected to the first capacitor thereby forming a current divider. The second capacitor carries a second current which is proportional to the first current. A transimpedance amplifier is connected to the second capacitor and has a voltage output that is proportional to the second current. Using a current feedback amplifier as the transimpedance amplifier significantly improves bandwidth and stability.

Abstract: A system and method for decoding video encoded using scalable video coding. In one embodiment, a decoder for scalable video coding (SVC) includes an SVC access unit analyzer and decoding logic. The SVC access unit analyzer is configured to examine an SVC access unit prior to layered decoding of the access unit, to determine, based on the examination, what operations the access unit specifies for each layer of the decoding, and to determine, based on the determined operations to be performed for each layer of the decoding, what data to store for use by a subsequent layer of the decoding. The decoding logic is configured to decode the access unit via a plurality of decoding layers; and to store at each decoding layer, for use by a subsequent decoding layer, the data determined by the SVC access unit analyzer to be used by the subsequent decoding layer.

Abstract: A circuit includes a state capture device to capture a logic state of a reset selection cell in response to a logic state input. A cell reset node defines a reset state of the reset selection cell. A selection device passes the captured logic state from the state capture device or the reset state from the cell reset node to an output of the reset selection cell based on a state of a control input to the selection device.

Abstract: A semiconductor device includes MOSFET cells having a drift region of a first conductivity type. A first and second active area trench are in the drift region. A split gate uses the active trenches as field plates or includes planar gates between the active trenches including a MOS gate electrode (MOS gate) and a diode gate electrode (diode gate). A body region of the second conductivity type in the drift region abutts the active trenches. A source of the first conductivity type in the body region includes a first source portion proximate to the MOS gate and a second source portion proximate to the diode gate. A vertical drift region uses the drift region below the body region to provide a drain. A connector shorts the diode gate to the second source portion to provide an integrated channel diode. The MOS gate is electrically isolated from the first source portion.

Abstract: The invention is directed to a method for inhibiting or preventing delamination at the interface of the die attach/mold compound and the die pad of a semiconductor device and a semiconductor device formed by such method. The method includes providing a leadframe having a top surface; coating the top surface of the leadframe with first and second silane coating; heating the silane coatings to form a porous layer having a porosity of at least 10%; applying a die to the porous layer; securing the die to the porous layer by a die attaching compound; and after the curing of die attach material and wire bonding, a mold compound is applied through molding.

Abstract: At least one tone is generated. An output signal is generated in response to an input signal and the at least one tone. The output signal is modulated. The input signal and the at least one tone are represented in the modulated output signal. The at least one tone is outside a bandwidth of the input signal as represented in the modulated output signal. The modulated output signal is amplified. The at least one tone in the amplified signal is attenuated after the amplifying.

Abstract: A dielectric wave guide (DWG) has a dielectric core member that has a first dielectric constant value. A cladding surrounding the dielectric core member has a second dielectric constant value that is lower than the first dielectric constant. A mating end of the DWG is configured for mating with a second DWG having a matching non-planar shaped mating end. A deformable material is disposed on the surface of the mating end of the DWG, such that when mated to a second DWG, the deformable material fills a gap region between the mating ends of the DWG and the second DWG.

Abstract: A power line communication (PLC) network includes a plurality of PLC devices. One such PLC device may include a transmitter power control system that determines a minimum level of transmission power for sufficiently communicating a plurality of data packets from the PLC device over the PLC network to a first destination PLC device on the PLC network by executing a training sequence over the PLC network via an electrical power distribution system. The transmitter power control system applies this minimum level of transmission power to transmit the data packets to the first destination PLC device.

Abstract: A material-discerning proximity sensor is arranged to include an antenna that is arranged to radiate a radio-frequency signal. A capacitive sensor is arranged to detect a change in capacitance of the capacitive sensor and to receive the radio-frequency signal. An electrical quantity sensor is arranged to detect a change of the received radio-frequency signal and a change of a radio-frequency signal at an output of the at least one band pass filter.

Abstract: A serial communication circuit (FIG. 3) is disclosed. The circuit includes an equalizer circuit (306) arranged to receive a data signal (CH 1) and produce an equalized data signal. A log detector circuit (300) receives the data signal and produces a power signal indicating a power level of the data signal. A decision circuit (332) receives the power signal and produces a select signal. A first selection circuit (336) receives a plurality of first correction signals and applies one of the first correction signals to the equalizer circuit in response to the select signal.

Abstract: An analog circuit for generating a periodic signal at a selected phase, including one or more phase interpolators that receive orthogonal differential RF signals and a pair of differential gain signals. The differential in-phase RF signal is applied at respective gates of tail transistors, and a first differential gain signal is applied across gates of a transistor pair coupled to each of the tail transistors. The quadrature-phase RF signal and a second differential gain signal is similarly applied to another quad of transistors (i.e., pair of transistor pairs) and associated tail transistors. A load connected to the one transistor in each pair receives the output signal, at a phase corresponding to a ratio of the first and second gain signals.

Abstract: A method of synchronizing includes providing a sensor network including sensor nodes having object recognition sensors (ORS's) and building automation network nodes. The ORS's have partially overlapping fields of view in a sensed overlap area in the building. Movement of an individual through the sensed overlap area triggers dynamic synchronizing with the first sensor node waking up and sending a first RF request to join a subnet and for a schedule of wakeup times, the first sensor node receiving a response from any sensor node that receives the first request including synchronization information having times the first sensor node should wake up. The second sensor node is activated by the individual's movement and sends a second RF message to join the subnet and for a schedule of wakeup times. The first sensor node receives the second RF message and in response sends the synchronization information to the second sensor node.

Abstract: Methods and apparatus for minimizing average quiescent current for a desire voltage error in a comparator are disclosed. An example method includes receiving a first voltage and a reference voltage, outputting a second voltage when the first voltage is lower than the reference voltage, wherein the outputting of the second voltage increases the first voltage, counting a number of clock cycles while the first voltage is higher than the reference voltage, comparing the number of clock cycles to a maximum number of clock cycles and a minimum number of clock cycles, when the number of clock cycles is above the maximum number of clock cycles, decreasing a frequency of a clock associated with the number of clock cycles, and when the number of clock cycles is below the minimum number of clock cycles increase the frequency of the clock.

Abstract: The disclosure provides an amplifier. The amplifier includes a first transistor that receives a first input. A second transistor receives a second input. A plurality of impedance networks is coupled between the first transistor and the second transistor. At least one impedance network of the plurality of impedance networks includes a first impedance path and a second impedance path. The first impedance path is activated during single ended operation, and the second impedance path is activated during differential operation.

Abstract: The approach shown provides for an efficient implementation of time response, level response and frequency response alignment between two audio sources such as DAB and FM that may be time offset from each other by as much as 2 seconds, and produces an aurally undetectable transition between the sources. Computational load is significantly reduced over the approaches known in the prior art.

Abstract: This invention sets conditions for user equipment responses to channel state indicator request in channel state information that may conflict.

Abstract: Frequency detector and oscillator circuits are disclosed. Example frequency detector and oscillator circuits disclosed herein include a current approximation circuit coupled to an external clock operating at a target frequency. In some examples, the current approximation circuit is configured to determine a magnitude of a first current to charge a capacitor to reach a reference voltage during a first set of clock cycles generated by the external clock. In some examples, the current approximation circuit is further configured to generate an output current based on the magnitude of the first current and to use the output current to produce a comparator output. In some examples, the frequency detector and oscillator circuits further include a latching circuit coupled to receive the comparator output from the current approximation circuit. In some such examples, the latching circuit is configured to generate oscillating signals at the target frequency based on the comparator output.

Abstract: Virtual boundary processing in adaptive loop filtering (ALF) requires that padded values be substituted for unavailable pixel rows outside the virtual boundaries. Methods and apparatus are provided for virtual boundary processing in ALF that allow the use of more actual pixel values for padding than in the prior art.