Abstract: A wireless device includes a preamble detector configured to identify preambles transmitted via a random access channel of a wireless network. The preamble detector includes preamble false alarm logic. The preamble false alarm logic is configured to set a preamble false alarm detection window, and compare, to one another, preambles identified in the false alarm detection window. The preamble false alarm logic is configured to identify, based on the comparison, a largest of the preambles in the false alarm detection window, and reject all but the identified largest of the preambles as false alarm detections.

Abstract: A Continuous Time Linear Equalizer (CTLE) and a method of operating a CTLE in a receiver for a Pulse Amplitude Modulation (PAM) signal are disclosed. The method includes initiating equalization using an initial equalization setting that is optimized to meet a first objective and responsive to a determination, shifting to a final equalization setting that is optimized to meet a second objective.

Abstract: A static random access memory (SRAM) includes an array of storage cells arranged as rows and columns and a read controller to manage reading from the storage cells. The array of storage cells includes word lines that correspond to the rows and bit lines that correspond to the columns. The read controller is configured to receive a precharge signal and a word line signal and identify consecutive reads from storage cells accessed via a same one of the word lines. The read controller is further configured to, based on the precharge signal and the word line pulse signal indicating that the SRAM is to operate in a partial burst mode, precharge the bit lines no more than once during the consecutive reads and charge the same one of the word lines after each read of the consecutive reads.

Abstract: Methods and apparatus to perform serial communications are disclosed. An example serial data transmitter includes: a clock signal generator to generate a digital clock signal; a clock signal controller to enable the clock signal generator; a line break signal generator to, in response to an expiration of a time period, trigger the transmission of a transmission line check frame; a data integrity check generator to generate error detection data corresponding to first data to be transmitted via the transmission port; a signal framer to: generate a first data frame having a preamble, second data, third data, the first data, the error detection data, and fourth data; and generate the transmission line check frame.

Abstract: Data transfer devices and methods for transferring data between first and second circuits are disclosed. A data transfer device includes a first circuit having a plurality of data channels, wherein at least one of the data channels is an active data channel. A serializer has a plurality of inputs and an output, wherein the inputs are coupled to the plurality of data channels. The serializer is for coupling only one active channel at a time to the output. An isolation barrier is coupled to the output of the serializer, the isolation attenuates transients and passes the fundamental frequency. A second circuit includes a deserializer having an input and at least one output, the input is coupled to the isolation barrier, the at least one output is at least one active data channel.

Abstract: An optical system includes an optical illumination source, an optical receiver, a correlation determination circuit, and an ambient condition control circuit. The optical illumination source is configured to emit a light in the direction of a target object. The optical receiver is configured to receive a combined optical signal that includes an ambient light component combined with an interrogation component. The correlation determination circuit is configured to compare the combined optical signal with an ambient light signal to identify a correlation factor. The ambient condition control circuit is configured to compare the correlation factor to a low correlation threshold value and a high correlation threshold value, and, based on the correlation factor exceeding the low threshold value and being less than the high correlation threshold value, cancel the ambient light component from the combined optical signal to produce an interrogation signal including the interrogation component.

Abstract: System and methods for input path matching in pipelined continuous-time Analog-to Digital Converters (ADCs), including pipelined Continuous-Time Delta Sigma Modulator (CTDSM) based ADCs, includes an input delay circuit disposed in a continuous-time input path from an input of an analog input signal to a first summing circuit of the continuous-time ADC. At least one digital delay line is disposed between an output of an earlier stage sub-ADC (of a plurality of pipelined sub-ADCs) and a sub-digital-to-analog converter (DAC) that is coupled to the first summing circuit, and between the earlier stage sub-ADC and a digital noise cancellation filter. The digital delay line(s) is configured to enable calibration of delay of output of the earlier stage sub-ADC provided to the sub-DAC and the digital noise cancellation filter in accordance with process variations of the input delay match circuit to minimize residue output at first summing circuit.

Abstract: Disclosed embodiments include a system having one or more member devices coupled to a network and a power line communication (PLC) device. The PLC device is configured to identify available bootstrapping agents that correspond to the one or more member devices, each available bootstrapping agent having a corresponding personal area network (PAN) identifier, identify a target network having a PAN identifier to join, select a target bootstrapping agent from available bootstrapping agents associated with the target PAN identifier to use for a join process with the target network, attempt to join the target network using the target bootstrapping agent, and when the attempt to join is successful, transmit and receive PLC signals over at least one power line associated with the target network using a particular frequency band and a modulation scheme.

Abstract: An adaptive driver includes a gate driver having at least one driving transistor for driving a control node of switching transistor(s) that includes an output node (OUT) which provides Vout. An adjustable current source is in series with the driving transistor, a high pass filter (HPF) is between OUT and ground for detecting a slew rate of the switching transistor and outputting a voltage pulse (Vslp) output having a peak voltage amplitude at least monotonically reflecting a slope of Vout during switching. Detection signal processing circuitry is coupled to the output of the HPF for processing Vslp and slew rate control circuitry has an input coupled to the output of the detection signal processing circuitry. The output of the slew rate control circuitry is coupled to the current source for controlling its current level for changing the slew rate of the switching transistor to provide a desired slew rate range.

Abstract: A device is configured for transmitting multiple channels of information through a dielectric waveguide (DWG). The device generates at least a first radio frequency signal (RF) and a second RF signal. The first RF signal is launched into the DWG using a launching structure formed within a multilayer substrate to excite a first transmission mode of the DWG. The second RF signal is launched into the DWG using a launching structure formed within the multilayer substrate to excite a second transmission mode of the DWG, in which the second transmission mode is orthogonal to the first transmission mode.

Abstract: In certain embodiments, methods and systems for multimedia data processing are provided. In an embodiment, a method for processing multimedia data includes defining one or more pixel block regions in a first cache so as to cache a plurality of reference pixel blocks corresponding to reference data. A reference pixel block from among the plurality of reference pixel blocks is assigned to a pixel block region from among the one or more pixel block regions based on a predetermined criterion. The reference pixel block is associated with a tag based on the pixel block region so as to facilitate a search of the reference data in order to process a plurality of pixel blocks associated with a multimedia frame of the multimedia data.

Abstract: Processors, systems, and methods are arranged to schedule tasks on heterogeneous processor cores. For example, a scheduler is arranged to perform a heuristics based function for allocating operating system tasks to the processor cores. The system includes a hint generator providing a system constraints-aware function that biases the scheduler to select a processor core depending on the change in one or more performance constraint parameters.

Abstract: A system comprises a plurality of components, scan chain selection logic coupled to the components, and override selection logic coupled to the scan chain selection logic. The scan chain selection logic selects various of the components to be members of a scan chain under the direction of a host computer. The override selection logic detects a change in the scan chain and, as a result, blocks the entire scan chain from progressing.

Abstract: A processor includes a plurality of execution units. At least one of the execution units is configured to execute a complex instruction that requires multiple instruction cycles to execute, and to enforce atomic execution of the complex instruction during a first-portion of the multiple instruction cycles required to execute the complex instruction. The at least one of the execution units is further configured to enable execution of the complex instruction to be interrupted for execution of a different instruction by the at least one execution unit during execution of a second portion of the multiple instruction cycles. The first portion and the second portion are non-overlapping.

Abstract: An electrostatic discharge (ESD) protection circuit includes a high power supply rail (VDD) and a low power supply rail (VSS). The ESD protection circuit further includes an active shunt transistor coupled between VDD and VSS. The active shunt transistor includes a gate. The ESD protection circuit also includes a sensing transistor connected between an input/output (I/O) pad and the gate of the active shunt transistor. If an ESD stress event occurs on the I/O pad or on a VDD pad, the sensing transistor is caused to be turned ON thereby permitting a voltage on the I/O or VDD pad experiencing the ESD stress event to turn ON the active shunt transistor in turn causing ESD current to flow from the pad experiencing the ESD event, through VDD, and through the active shunt transistor to VSS.

Abstract: A method of acquiring a satellite signal in a GNSS receiver includes multiplying a received signal with a hypothesized doppler frequency signal to generate a frequency shifted signal. A PN code sequence signal is multiplied with the frequency shifted signal to generate a PN wiped signal. A windowing function signal is multiplied with the PN wiped signal to generate a windowed signal. The windowed signal is integrated coherently for a first predefined time to generate a coherent accumulated data.

Abstract: Control logic for producing a digital input to a digital-to-analog converter (DAC) in a power converter system. The control logic selects from among a plurality of slew rates during a transition of an output voltage in response to a change in the desired setpoint, so that the output voltage transition follows a desired nominal slew rate. In an initial interval of the transition, a steeper slew rate than the nominal slew rate is selected by the control logic for the digital input to the DAC, until the digital input to the DAC exceeds the nominal slew rate by a first parameter value. At that point, a slew clamp is applied to advance the digital input at the nominal slew rate. Upon the digital input approaching the setpoint value to within a second parameter value, a flatter slew rate than nominal is applied.

Abstract: A device operated in a network using a channel hopping communication protocol may select a channel for each transmission by first generating and storing a sequence of pseudo-random index numbers. A list of good channels is selected from a plurality of channels. For each channel hop, one of the good channels is selected from the list of good channels for use by a transceiver in the device by using an index number selected from the sequence of pseudo-random index numbers. The list of good channels may be revised periodically and channels may be selected from the list of good channels for use by the transceiver without revising the sequence of pseudo-random index numbers.

Abstract: The disclosure provides a novel method and apparatus for inputting addresses to devices to select the device TAP for access. Further, the disclosure provides a novel method and apparatus for inputting addresses for selecting device TAPs and for inputting commands for commanding circuitry within the device. The inputting of addresses or the inputting of addresses and commands is initiated by a control bit input on TDI that is recognized during the Run Test/Idle, Pause-DR or Pause-IR TAP states.

Abstract: A GNSS receiver configured to detect a presence of at least one GNSS satellite signal in a received signal is provided. The GNSS receiver includes a buffer loaded with sample sets corresponding to the received signal and a Doppler derotation block configured to perform a Doppler derotation corresponding to at least one Doppler frequency on a sample set received from the buffer. The GNSS receiver further includes an accumulator block configured to perform a coherent accumulation of a plurality of sample sets upon or subsequent to the Doppler derotation corresponding to a Doppler frequency, and, a first memory configured to store the results of the coherent accumulation. A register array is configured to be loaded with the results stored in the first memory and a correlator engine is configured to generate correlation results by correlating the results in the register array with a plurality of code phases of GNSS satellites.