Abstract: Digital data are recovered from a clocked serial input signal. The input signal is sampled with a sampling clock signal supplied by a first phase interpolator to obtain a sampled digital signal. The first phase interpolator is controlled with a voting circuit to adjust the phase of the sampling clock relative to the eye in the eye-diagram of the input signal. The first phase interpolator has signal inputs connected to signal outputs of a voltage controlled oscillator in a phase-locked loop circuit that has a reference signal input to which the reference clock signal is applied. The sampled digital signal is written to a single-bit FIFO buffer with a write clock signal that has the same timing as the sampling clock. A filtered output signal is read from the FIFO buffer with a read clock signal supplied by a second phase interpolator that has signal inputs connected to the signal outputs of the voltage controlled oscillator in the phase-locked loop.

Abstract: System and method for limiting an output signal of a differential amplifier. A preferred embodiment comprises a limit sense amplifier configured to detect when the output exceeds a permitted limit, a common mode bias current unit configured to increase a signal gain of a common mode amplifier in the differential operational amplifier when the limit sense amplifier detects that the output exceeded the permitted limit, and an output stage bias current unit configured to fix the output at a level substantially equal to the specified limit when the limit sense amplifier detects that the output exceeded the permitted limit. The clamping is achieved by changing the operation of circuitry within the differential amplifier and results in a smoother clamping that helps to maintain stable operation.

Abstract: Timely testing of die on wafer reduces the cost to manufacture ICs. This disclosure describes a die test structure and process to reduce test time by adding test pads on the top surface of the die. The added test pads allow a tester to probe and test more circuits within the die simultaneously. Also, the added test pads contribute to a reduction in the amount of test wiring overhead traditionally required to access and test circuits within a die, thus reducing die size.

Abstract: A method for selective deposition of self-assembled monolayers to the surface of a substrate for use as a diffusion barrier layer in interconnect structures is provided comprising the steps of depositing a first self-assembled monolayer to said surface, depositing a second self-assembled monolayer to the non-covered parts of said surface and subsequently heating said substrate to remove the first self-assembled monolayer. The method of selective deposition of self-assembled monolayers is applied for the use as diffusion barrier layers in a (dual) damascene structure for integrated circuits.

Abstract: In one aspect of the invention, a method for forming an integrated circuit having an at least substantially doped porous dielectric includes forming a semiconductor device. The semiconductor device includes at least a portion of a semiconductor substrate. The method also includes forming a dielectric layer disposed outwardly from the semiconductor substrate and surrounding at least a portion of the semiconductor device. The dielectric layer includes an at least substantially porous dielectric material doped with at least one dopant. In addition, the method includes forming a contact layer disposed outwardly from the dielectric layer and operable to provide electrical connection to the semiconductor device.

Abstract: Disclosed herein is a method of manufacturing a semiconductor package with a solder standoff on lead pads that reach to the edge of the package (non-pullback leads). It includes encapsulating a plurality of die on a lead frame strip. The lead frame strip comprises a plurality of package sites, which further comprises a plurality of lead pads and a die pad. The method also includes forming a channel between the lead pads of nearby package sites without singulating the packages. Another step in the method includes disposing solder on the lead pads, the die pad, or the lead pads and the die pads without substantially covering the channel with solder. The manufacturing method further includes singulating the packages.

Abstract: The present invention provides an integrated virtual voltage circuit for use with a sub-circuit. In one embodiment, the integrated virtual voltage circuit includes a MOS transistor switch coupled to a supply voltage and configured to employ a drain to provide an operating voltage for the sub-circuit during switch activation. Additionally, the integrated virtual voltage circuit also includes a connection unit coupled to the MOS transistor switch and configured to provide a standby voltage for the sub-circuit during deactivation of the MOS transistor switch wherein the standby voltage is based on a static coupling of the drain to a body region of the MOS transistor switch. In an alternative embodiment, the connection unit is further configured to connect a voltage reference between the supply voltage and the drain of the MOS transistor switch to determine the standby voltage.

Abstract: The objective of this invention is to provide a photodiode which has high sensitivity even to light with a wavelength in the blue region while maintaining the high-frequency characterstics. The n type second semiconductor layer (13) containing an n type electroconductive impurity at a low concentration is formed directly or via an intrinsic semiconductor layer (11) on the p type first semiconductor layer (10). The third semiconductor layer (20) containing an n type electroconductive impurity at a medium concentration is formed shallower than said second semiconductor layer (13) in its main plane. The fourth semiconductor layer (21) containing an n type electroconductive impurity at a high concentration is formed shallower than said third semiconductor layer (20) in the main plane of the third semiconductor layer (20).

Abstract: Data speed in an I2C system is increased by operating a master CPU (110) to pipeline a stop/start/address byte transfer instruction by setting a stop bit, setting a start bit, and storing an address byte, operating a control circuit (87) in response to the stop bit to automatically send a stop condition on the I2C bus, operating a timing circuit (40) to count a predetermined delay from the stop condition, and operating the control circuit (87) in response to the start bit to automatically send a start condition on I2C bus after the delay has elapsed. The control circuit (87) automatically sends the address byte on the I2C bus after the start condition has been sent.

Abstract: Hysteresis circuit 10 is composed of three inverters 40, 42, 44. Node NB in hysteresis circuit 10 is connected to the input terminal of transition-detecting part 14 of transmission control part 12. Transition-detecting part 14 detects the timing of the start of the output inversion operation and the timing of the completion of the transition in hysteresis circuit 10 corresponding to potential VB of node NB, and it controls activation/deactivation of inverter 50 on the signal transmission path.

Abstract: A method of tilting a micromirror includes forming a substrate, a micromirror outwardly from the substrate, and at least one electrode inwardly from the micromirror. The method further includes applying, by the at least one electrode, electrostatic forces sufficient to pivot the micromirror about a pivot point. In addition, the method includes providing the at least one electrode with a sloped outer surface. The sloped outer surface has a first end and a second end. The second end is closer to the pivot point than the first end, and the first end is closer to the substrate than the second end. The method also includes providing at least a portion of the at least one electrode with material properties that at least partially contribute to the sloped profile of the sloped outer surface.

Abstract: An apparatus and method to test components in a semiconductor test structure. On a semiconductor wafer, a test module implemented in one or more scribe lines between a plurality of semiconductor dies is used to test components in the semiconductor test structure. The test module may, for example, test electrical characteristics of chains of vias, transistors, and functional devices, such as oscillators. The test module contains a scan chain control coupled through a plurality of pass gates to each component to be tested. The scan chain control sequentially closes the pass gates to separately test the components in the semiconductor test structure. The test module further interfaces with an external testing device and the results of each test are compared with the expected results to identify faulty components.

Abstract: A mobile communication system is designed with an input circuit coupled to receive a first plurality of signals (rj(i+?j), i=0?N?1) during a first time (T0-T1) from an external source and coupled to receive a second plurality of signals (rj(i+?j), i=N?2N?1) during a second time (T1-T2) from the external source. The input circuit receives each of the first and second plurality of signals along respective first and second paths (j). The input circuit produces a first input signal (Rj1) and a second input signal (Rj2) from the respective first and second plurality of signals. A correction circuit is coupled to receive a first estimate signal (?j1), a second estimate signal (?j2) and the first and second input signals. The correction circuit produces a first symbol estimate ( S1) in response to the first and second estimate signals and the first and second input signals.

Abstract: A method for characterizing a load on a data line includes the steps of: (A) Applying at least three successive voltages to the data line. Each respective odd-numbered successive voltage of the at least three successive voltages has substantially a first voltage value displaced a first voltage interval from a reference voltage value. Each respective even-numbered successive voltage of the at least three successive voltages has substantially a second voltage value displaced a second voltage interval from the reference voltage value. (B) Measuring a respective current value on the data line while each of the at least three successive voltages is applied to the data line. (C) Comparing the respective current values for selected successive voltages of the at least three successive voltages to determine whether a hysteric impedance change occurs when voltage on the data line is varied.

Abstract: A method for generating and evaluating a table model for circuit simulation in N dimensions employing mathematical expressions for modeling a device. The table model uses an unstructured N-dimensional grid for approximating the expressions.

Abstract: An enhanced noise pre-processor in a speech codec smoothes channel energy estimate moving toward a first smoothing constant if a prior signal to noise ratio estimate for more than five channels are above a threshold and toward a second smaller smoothing constant otherwise. Forming a signal to noise ratio estimate for each channel includes conditionally boosting if a signal energy estimate is more than a predetermined factor of a noise energy estimate and signal to noise ratio estimates are above a threshold for more than five channels. The estimated signal to noise ratio is conditionally modified if two long term prediction coefficients are above a predetermined factor. The estimated signal to noise ratio is not modified and a voice metric is set greater than a voice metric threshold upon matching templates corresponding to the fricative and nasal speech sounds. An adaptive minimum channel gain is chosen based on a current signal to noise ratio estimate.

Abstract: A novel hybrid stochastic gradient adaptation apparatus and method for calibrating the gain of an RF or non-RF digitally controlled oscillator (DCO). The adaptation algorithm determines a true stochastic gradient between a forcing function and its corresponding system measure to estimate the system parameters being adapted. A momentum term is generated and injected into the adaptation algorithm in order to stabilize the algorithm by adding inertia against any large transient variations in the input data. In the case of adaptation of DCO gain KDCO, the algorithm determines the stochastic gradient between time varying calibration or actual modulation data and the raw phase error accumulated in an all digital phase locked loop (ADPLL). Two filters preprocess the observable data to limit the bandwidth of the computed stochastic gradient providing a trade-off between sensitivity and settling time.

Abstract: A vector-based sequence generator (100) provides for a general architecture that can be easily adapted to any random length sequence and any random number of bits per access. The sequence generator (100) can also produce a new access on every hardware clock cycle, thereby maximizing the efficiency of the bit sequence requesting process.

Abstract: A method for transmitting light in an image display system includes generating a first cone of light from a first light source. The first cone of light includes a plurality of light beams. A first portion of the first cone is projected in an illumination path. A second portion of the first cone is projected at a surface of a reflector. The second portion of the first cone is reflected to project the second portion of the first cone in the illumination path. The first and second portions of the first cone are received at an entrance of an integrator rod. The second portion of the first cone increases the intensity of light received by the integrator rod.

Abstract: Embodiments of the present disclosure provide a power-optimizing memory analyzer, a method of operating a power-optimizing memory analyzer and a memory system employing the analyzer or the method. In one embodiment, the power-optimizing memory analyzer is for use with an array of memory blocks and includes a task database configured to provide a parameter set corresponding to each of a set of tasks to be performed in a system. The power-optimizing memory analyzer also includes an allocation module configured to determine offline, a group of memory blocks in the array corresponding to the parameter set for each task and based on providing a power reduction for the array. The power-optimizing memory analyzer further includes a power profiling module configured to generate run-time power profiles of memory power states for each task allowing transparent and dynamic control of the memory power states while maintaining a required quality of service.