Abstract: Dimensions of structures in integrated circuits are shrinking with each new fabrication technology generation. Maintaining control of profiles of structures in transistors and interconnects is becoming more important to sustaining profitable integrated circuit production facilities. Measuring profiles of structures with many elements in integrated circuits, such as MOS transistor gates with recessed regions for Si—Ge epitaxial layers, is not cost effective for the commonly used metrology techniques: SEM, TEM and AFM. Scatterometry is technically unfeasible due to the number of elements and optical constants. The instant invention is a simplified scatterometry structure which reproduces the profiles of a structure to be profiled in a simpler structure that is compatible with conventional scatterometric techniques. A method of fabricating a transistor and an integrated circuit using the inventive simplified scatterometry structure are also disclosed.

Abstract: A method for contacting MOS devices. First openings in a photosensitive material are formed over a substrate having a top dielectric in a first die area and a second opening over a gate stack in a second die area having the top dielectric, a hard mask, and a gate electrode. The top dielectric layer is etched to form a semiconductor contact while etching at least a portion the hard mask layer thickness over a gate contact area exposed by the second opening. An inter-layer dielectric (ILD) is deposited. A photosensitive material is patterned to generate a third opening in the photosensitive material over the semiconductor contact and a fourth opening inside the gate contact area. The ILD is etched through to reopen the semiconductor contact while etching through the ILD and residual hard mask if present to provide a gate contact to the gate electrode.

Abstract: An embodiment of the invention provides a method of creating a statistical model of a baseline capacitance CP of a capacitive sensor located on a capacitive-touch screen. A sensed capacitance CS of a capacitive sensor is measured during a particular state of the electronic device that includes the capacitive-touch screen. When physical contact is not made with the capacitive sensor, the sensed capacitance CS is stored as a baseline capacitance CP. The baseline capacitance CP is then used to create the statistical model for that particular state of the electronic device. When physical contact is made with the capacitive sensor, the value of the baseline capacitance CP of the capacitive sensor is subtracted from the value of the sensed capacitance CS and the result, CF=(CS?CP), is sent to a touch detection circuit.

Abstract: An integrated circuit includes isolation capacitors which include a silicon dioxide dielectric layer and a polymer dielectric layer over the layer of silicon dioxide. The silicon dioxide dielectric layer and the polymer dielectric layer extend across the integrated circuit. Top plates of the isolation capacitors have bond pads for wire bonds or bump bonds. Bottom plates of the isolation capacitors are connected to components of the integrated circuit. Other bond pads are connected to components in the integrated circuit through vias through the silicon dioxide dielectric layer and the polymer dielectric layer.

Abstract: A semiconductor device containing an NPN bipolar junction transistor may be formed by forming a p-type radiation induced diode structure (RIDS) region in an intrinsic p-type base region of the NPN bipolar junction transistor at a boundary of the intrinsic p-type base region with a dielectric layer over a substrate of the semiconductor device, between an emitter of the NPN bipolar junction transistor and an extrinsic p-type base region of the NPN bipolar junction transistor. The p-type RIDS region has a doping density high enough to prevent inversion of a surface of the p-type RIDS region adjacent to the dielectric layer when trapped charge is accumulated in the dielectric layer, while the intrinsic p-type base region may invert from the trapped charge forming the radiation induced diode structure. The p-type RIDS region is separated from the emitter and from the extrinsic base region by portions of the intrinsic base region.

Abstract: Within a wireless network, feedback information from user equipment (UE) to a control node (eNodeB) is necessary to support various functions. A UE receives an allocation from the eNodeB comprising a plurality of periodic transmission instances for a channel quality indicator (CQI) and a schedule comprising a plurality of periodic transmission instances for a rank indicator (RI), wherein the CQI comprises RI and other CQI fields. The UE then transmits an RI without transmitting the other CQI fields in a transmission instance allocated for both RI and other CQI fields.

Abstract: A prefetch unit receives a memory read request having an associated address for accessing data that is stored in memory. A next predicted address is determined in response to a prefetch address stored in a slot of an array for storing portions of predicted addresses and associated with a slot in accordance with an order in which a prefetch FIFO counter is modified to select the slots of the array. Data is prefetched from a lower-level hierarchical memory in accordance with a next predicted address and provisioned the prefetched data to minimize a read time for reading the prefetched data. The provisioned prefetched data is read-out when the address of the memory request is associated with the next predicted address.

Abstract: An electronic isolation device is formed on a monolithic substrate and includes a plurality of passive isolation components. The isolation components are formed in three metal levels. The first metal level is separated from the monolithic substrate by an inorganic PMD layer. The second metal level is separated from the first metal level by a layer of silicon dioxide. The third metal level is separated from the second metal level by at least 20 microns of polyimide or PBO. The isolation components include bondpads on the third metal level for connections to other devices. A dielectric layer is formed over the third metal level, exposing the bondpads. The isolation device contains no transistors.

Abstract: A process of forming an integrated circuit containing a piezoelectric thin film by forming a sol gel layer, drying in at least 1 percent relative humidity, baking starting between 100 and 225° C. increasing to between 275 and 425° C. over at least 2 minutes, and forming the piezoelectric thin film by baking the sol gel layer between 250 and 350° C. for at least 20 seconds, annealing between 650 and 750° C. for at least 60 seconds in an oxidizing ambient pressure between 700 and 1000 torr and a flow rate between 3 and 7 slm, followed by annealing between 650 and 750° C. for at least 20 seconds in a pressure between 4 and 10 torr and a flow rate of at least 5 slm, followed by ramping down the temperature.

Abstract: A semiconductor device has a vertical drain extended MOS transistor with deep trench structures to define a vertical drift region and at least one vertical drain contact region, separated from the vertical drift region by at least one instance of the deep trench structures. Dopants are implanted into the vertical drain contact regions and the semiconductor device is annealed so that the implanted dopants diffuse proximate to a bottom of the deep trench structures. The vertical drain contact regions make electrical contact to the proximate vertical drift region at the bottom of the intervening deep trench structure. At least one gate, body region and source region are formed above the drift region at, or proximate to, a top surface of a substrate of the semiconductor device. The deep trench structures are spaced so as to form RESURF regions for the drift region.

Abstract: A semiconductor device having a vertical drain extended MOS transistor may be formed by forming deep trench structures to define vertical drift regions of the transistor, so that each vertical drift region is bounded on at least two opposite sides by the deep trench structures. The deep trench structures are spaced so as to form RESURF regions for the drift region. Trench gates are formed in trenches in the substrate over the vertical drift regions. The body regions are located in the substrate over the vertical drift regions.

Abstract: An integrated circuit (IC) includes a plurality of input/output (I/O) terminals through which signals pass into or out of the IC and an I/O timing module. The I/O timing module is configured to add propagation delay to signals passing between the I/O terminals and I/O subsystems of the IC. The I/O timing module includes a plurality of delay elements associated with each of the I/O terminals, a control register associated with each of the I/O terminals, a memory, and I/O delay control logic. The control register is coupled to each of the delay elements associated with the I/O terminal. The memory is encoded with delay information. The I/O delay control logic is configured to initialize the propagation delay associated with each of the I/O terminals by selecting which of the delay elements are to be applied to produce the propagation delay based on the delay information stored in the memory.

Abstract: A packet header protection system includes, for example, a header checksum (CS) that is arranged to provide error detection capability to FSK (frequency shift keyed) packet headers. Accordingly, receivers in the network can more quickly terminate processing of an errored packet upon detection of error(s) in the header. Quickly detecting packet header errors helps to avoid a sequence of compounding errors such as the repeated transmissions of a packet having an undetected erroneous header. Accordingly, the packet header protection system reduces false alarm rate in the network and increases network throughput.

Abstract: A serial bus network includes a voltage regulator, a plurality of power switches, and a voltage monitor. The voltage regulator provides power to a plurality of serial buses. Each of the serial buses provides power from the voltage regulator to a device coupled to the serial bus. Each of the power switches switches power from the voltage regulator to one of the serial buses, and includes an input terminal coupled to a voltage regulator output, and an output terminal coupled to one of the serial buses. The voltage monitor is coupled to the voltage regulator and to the output terminal of each of the power switches. The voltage monitor compares bus voltages at the output terminals of the power switches, identifies a lowest of the bus voltages, and adjusts the voltage regulator output voltage such that the identified lowest of the bus voltages is within a predetermined operational voltage range.

Abstract: Embodiments of the invention provide systems and methods for a cipher then segment approach in a Power Line Communication (PLC). A node or device generates frames to be transmitted to a destination node in the PLC network. A processor in the node is configured to generate a data payload comprising data to be sent to the destination node. The processor divides the data payload into two or more payload segments and encrypts the payload segments. The processor creates a frame for each of the encrypted payload segments, wherein each frame comprises a message integrity code. The processor creates a segment identifier for each frame using the message integrity code and an authentication key that is shared with the destination PLC node. The segment identifier is added to each frame.

Abstract: A capacitance detection circuit detects changes in the capacitance of a variable capacitor by using the change in capacitance to change the resonant frequency of a variable capacitor oscillator. The resonant frequency of the variable capacitor oscillator is converted from the time domain to the frequency domain, and then selected frequencies values are compared to known frequency domain values to detect the magnitude of the change in capacitance.

Abstract: A semiconductor device having a vertical drain extended MOS transistor may be formed by forming deep trench structures to define at least one vertical drift region bounded on at least two opposite sides by the deep trench structures. The deep trench structures include dielectric liners. The deep trench structures are spaced so as to form RESURF regions for the drift region. Vertical gates are formed in vertically oriented gate trenches in the dielectric liners of the deep trench structures, abutting the vertical drift regions. A body implant mask for implanting dopants for the transistor body is also used as an etch mask for forming the vertically oriented gate trenches in the dielectric liners.

Abstract: Methods for reconfiguring an ASIC at runtime without using voltage over scaling. A functional criticality of a set of logic in the ASIC is identified. Then, the set of logic are classified into a set of regions based on the functional criticality, each region of the set of regions having a target error threshold. Further, each region is power gated at runtime based on the functional criticality such that the target error threshold is achieved without using voltage over scaling.

Abstract: A system and method for controlling operation of a pipeline. In one embodiment, a pipelined datapath includes a plurality of processing stages and a pipeline controller. Each of the processing stages is configured to further processing provided by a previous one of the processing stages. The pipeline controller is configured to control operation of the processing stages. The pipeline controller includes a pipelined finite state machine. The pipelined finite state machine includes a plurality of control stages. Each of the control stages is configured to control operation of a single one of the processing stages, and to receive a state value that defines a state of the control stage for controlling the single one of the processing stages from a previous control stage.

Abstract: A transmitter used in a communication system includes a raised cosine filter for transmit pulse shaping. A receiver in the communication system, designed to receive and demodulate transmissions from the transmitter, includes a root-raised cosine filter for receive pulse shaping. The use of a raised cosine filter in the transmitter enables reduction of peak-to-average ratio (PAR) of the output of a power amplifier used in the transmitter, enabling the power amplifier to be implemented to have relatively higher power efficiency than otherwise. In an embodiment, the transmitter and receiver employ ?/2-shift binary phase-shift keying (?/2 BPSK), and the raised cosine filter in the transmitter is implemented to have a roll-off factor of 0.5 and a total length of four symbol periods. In an embodiment, the root-raised cosine filter is implemented to have a roll-of factor of 0.2 and a length of four symbol periods.