Abstract: A wireless power receiver receives electrical power via electromagnetic field coupling from a wireless power transmitter. During communication time periods, the power receiver alters the electromagnetic field in a manner that the power transmitter can detect as a string of logic bits in a communication bit stream for sending data to the power transmitter. During pause time periods when data is not being sent to the power transmitter, the power receiver alters the electromagnetic field in a manner that the power transmitter does not detect as a string of logic bits (e.g. at a rate outside a communication frequency band). In some embodiments, a ripple is reduced in a voltage produced by the wireless power receiver from the electromagnetic field during the communication and pause time periods.

Abstract: Embodiments of the disclosure provide a cross coupled position engine architecture for sensor integration in a Global Navigation Satellite System. In one embodiment, a data processing engine for processing inertial sensor data within a positioning system receiver is disclosed. The data processing engine includes a first input for receiving the sensor data, and a second input for receiving a positioning data. The data processing system also includes a memory and a processor. The processor of the data processing system is coupled to the memory and to the first and second input. The processor of the data processing system is configured to calculate a net acceleration profile data from the inertial sensor data and from the positioning data. The net acceleration profile data calculated by the processor of the data processing system is used for the Global Positioning System (GPS) receiver to subsequently calculate a position and a velocity data.

Abstract: An integrated circuit containing linear structures on regular pitch distances may be formed by forming linear mandrels over a layer of material for the linear structures, with mandrel pitch distances that are twice the desired linear structures' pitch distances. Mandrels for a first plurality of linear structures are shortened. A layer of spacer material is conformally formed over the mandrels and anisotropically etched back to form spacers on lateral surfaces of the mandrels. Spacers on the shortened mandrels are narrower than spacers on the unshortened mandrels as a result of the anisotropic etchback. The mandrels are removed, leaving the spacers in place to form a spacer-based etch mask for the linear structures. The layer of material for the linear structures is etched using the spacer-based etch mask to form the linear structures. The linear structures from the shortened mandrels have lower widths than the linear structures from the unshortened mandrels.

Abstract: Various exemplary embodiments provide probes, systems and methods for measuring an effective electrical resistance/resistivity with high sensitivity. In one embodiment, the measuring system can include an upper probe set and a similar lower probe set having a sample device sandwiched there-between. The device-under-test (DUT) samples can be sandwiched between two conductors of the sample device. Each probe set can have an inner voltage sense probe coaxially configured inside an electrically-isolated outer current source probe that has a large contact area with the sample device. The measuring system can also include a computer readable medium for storing circuit simulations including such as FEM simulations for extracting a bulk through-plane electrical resistivity and an interface resistivity for an effective electrical z-resistivity of the DUT, in some cases, having sub-micro-ohm resistance.

Abstract: An integrated circuit includes a detector configured to monitor a high-drive signal and a low-drive signal that drives a high-side switch and a low-side switch respectively of an integrated circuit switching regulator. The detector monitors both the rising edge and the trailing edge of each of the high-drive and the low-drive signals respectively to determine a timing overlap between the signals and generates a detection signal indicating a dead-time value proportional to the presence or absence of the timing overlap between the signals. An output circuit can be configured to process the detection signal from the detector to enable a correction of the timing overlap between the signals if timing overlap is detected.

Abstract: A system having a plurality of application computer circuits is disclosed. A first application computer circuit is arranged to process a first application. A trace collection circuit collects trace information from the first application computer circuit. A second application computer circuit is arranged to receive and store the collected trace information in a first mode and to process a second application in a second mode.

Abstract: A DCDC converter includes a transconductance amplifier, a comparator, a current driving component, an output impedance, a switch, a clamp resistor and a p-channel FET. The transconductance amplifier outputs a transconductance current and a switch control signal. The comparator has a two n-channel FET inputs forming a differential pair and outputs a compared signal. The current driving component generates an output current based on the compared signal. The output impedance component generates an output DC voltage based on the output current. The switch is between the two n-channel FETs and can open and close based on the switch control signal. The clamp resistor is arranged in series with the switch. The p-channel FET is in series with the clamp resistor and is controlled by the output DC voltage.

Abstract: A method for a processor computing a first trigonometric function to use an alternative trigonometric function for certain ranges of the operand. A modulo function may be used to provide an operand with a reduced range, and the modulo function may subtract in multiple steps in a manner that preserves low-order bits.

Abstract: In an embodiment, a circuit includes a Direct Current (DC)-DC buck-boost converter and a controller. The controller includes an error amplifier configured to receive a feedback signal responsive to an output signal of the buck-boost converter. The error amplifier is configured to compare the feedback signal and a reference signal to generate an error signal. The controller includes a modulator circuit that is configured to receive the error signal and compare the error signal with a periodic ramp signal to generate a modulated signal. The controller further includes a digital logic block to generate switching signals in response to the modulated signal that is fed to the buck-boost converter to control the output signal of the buck-boost converter. The controller includes a capacitance multiplier circuit coupled to the output of the error amplifier to configure a dominant pole so as to compensate the buck-boost converter.

Abstract: A method of operating a time division duplex (TDD) wireless communication system is disclosed. The method includes establishing communications with a remote transceiver. A subframe configuration including static and flexible subframes is determined and transmitted to the remote transceiver. A channel state information (CSI) report is received from the remote transceiver in response to the subframe configuration.

Abstract: A method of peak detection applicable to complex in-phase and quadrature phase signals in a digital radio receiver where the incoming signal is divided into a plurality of frames. Each frame is then further divided into a plurality of smaller blocks, and the signal peak is determined in each block individually followed by selecting the peak signal value from the said blocks.

Abstract: A power supply unit includes a boost converter having an input node and output node. The output node is coupled to a high-side of an H-bridge that is for supplying power to a capacitive load that is coupled to a first node and to a second node of the H-bridge. A first diode is coupled in forward direction between the first node of the H-bridge and the input node of the boost converter. A second diode is coupled in forward direction between the second node of the H-bridge and the input node of the boost converter.

Abstract: A digital circuit includes at least one input node, a biasing circuit, and a digital baseband circuit. The input node receives a digital signal including samples at a plurality of sample instances, the samples including a positive sample and a negative sample and represented by first plurality of bits. The biasing circuit generates a biased digital signal by adding a bias value to the digital signal so as to change the positive sample and the negative sample to first sample and second sample respectively and represented by second plurality of bits. The digital baseband circuit is configured to receive and process the biased digital signal such that reduced current consumption is realized based on a number of bit toggles in the second plurality of bits being less than a number of bit toggles in the first plurality of bits.

Abstract: According to one embodiment of the present invention, a system for illuminating a target includes a light source configured to emit one or more light beams with a first divergence. The system further includes a lens separated from the light source. The lens is configured to substantially satisfy the sine condition without removing spherical aberrations from the one or more light beams. The lens is further configured to receive the one or more light beams with the first divergence. The lens is further configured to change the first divergence of the one or more light beams to a second divergence. The second divergence is less than the first divergence. The second divergence is greater than zero. The lens is further configured to transmit the one or more light beams with the second divergence.

Abstract: A micro-fabricated atomic clock structure is thermally insulated so that the atomic clock structure can operate with very little power in an environment where the external temperature can drop to ?40° C., while at the same time maintaining the temperature required for the proper operation of the VCSEL and the gas within the vapor cell.

Abstract: An integrated circuit may be formed by forming a first interconnect pattern in a first plurality of parallel route tracks, and forming a second interconnect pattern in a second plurality of parallel route tracks, in which the second plurality of route tracks are alternated with the first plurality of route tracks. The first interconnect pattern includes a first lead pattern and the second interconnect pattern includes a second lead pattern, such that the route track containing the first lead pattern is immediately adjacent to the route track containing the second lead pattern. Metal interconnect lines are formed in the first interconnect pattern and the second interconnect pattern. A stretch crossconnect is formed in a vertical connecting level, such as a via or contact level, which electrically connects only the first lead and the second lead. The stretch crossconnect is formed concurrently with other vertical interconnect elements.

Abstract: Embodiments of the present disclosure provide a transmitter, a receiver and methods of operating a transmitter or a receiver. In one embodiment, the transmitter is for use with a base station and includes a primary module configured to provide a primary synchronization signal. The transmitter also includes a secondary mapping module configured to provide a secondary synchronization signal derived from two sequences taken from a same set of N sequences and indexed by an index pair (S1, S2) with S1 and S2 ranging from zero to N?1, wherein the index pair (S1, S2) is contained in a mapped set of index pairs corresponding to the same set of N sequences that defines a cell identity group. Additionally, the transmitter further includes a transmit module configured to transmit the primary and secondary synchronization signals.

Abstract: Several systems, methods and integrated circuits capable of reducing blocking artifacts in video data are disclosed. In an embodiment, a system for reducing blocking artifacts in video data includes a processing module and a deblocking module. The deblocking module comprises a luma deblocking filter and a chroma deblocking filter configured to filter an edge between adjacent blocks associated with the video data, where a block of the adjacent blocks corresponds to one of a prediction block and a transform block. The processing module is communicatively associated with the deblocking module and is operable to configure at least one filter coefficient corresponding to the chroma deblocking filter based on one or more filter coefficients corresponding to the luma deblocking filter. The processing module is further configured to cause the chroma deblocking filter to filter the edge between the adjacent blocks based on the configured at least one filter coefficient.

Abstract: The approach shown provides for an efficient implementation of time response, level response and frequency response alignment between two audio sources such as DAB and FM that may be time offset from each other by as much as 2 seconds, and produces an aurally undetectable transition between the sources. Computational load is significantly reduced over the approaches known in the prior art.

Abstract: Systems and methods and resulting compositions of matter including silicon solids from a mixture of silicon and water. The mixture is collected at a collection stage from at least one wafer abrasion process performed on a silicon surface having an impurity concentration ?0.1 ppb and extracting one portion of the water from the mixture using at least one dryer stage to form a dry cake. The dry cake includes at least 99.99% silicon by weight excluding water and non-silicon species, where a concentration of water in the dry cake is between 0.05% and 1% by weight, and where a concentration of non-silicon species in the dry cake is between 0.05% and 1% by weight.