Abstract: The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the semiconductor device. The semiconductor device (100), among other possible elements, includes a gate oxide (140) located over a substrate (110), and a silicided gate electrode (150) located over the gate oxide (140), wherein the silicided gate electrode (150) includes a first metal and a second metal.

Abstract: The present invention provides a tunable voltage controller for use with a sub-circuit. In one embodiment, the tunable voltage controller includes a diode-connected MOS transistor contained in a doped well of a substrate and configured to provide a voltage for the sub-circuit. Additionally, the tunable voltage controller also includes a biasing unit configured to adjust the voltage by selectively connecting the doped well to one of a plurality of voltage sources or to a variable voltage source.

Abstract: The invention provides a method for manufacturing a microelectronic device and a microelectronic device. The method for manufacturing the microelectronic device, without limitation, may include forming a first mirror layer over and within one or more openings in a sacrificial spacer layer, and forming a dielectric layer over an upper surface of the first mirror layer and within the one or more openings. The method may further include subjecting the dielectric layer to an etch, the etch removing the dielectric layer from the upper surface and leaving dielectric portions along sidewalls of the one or more openings, and forming a second mirror layer over the first mirror layer and within the one or more openings, the dielectric portions separating the first mirror layer and the second mirror layer along the sidewalls.

Abstract: Generating an output signal having a frequency of 1/(M+F) of the frequency of the input signal, wherein M represents an integer and F represents a non-zero fraction. Assuming F equals (Q/R) in one embodiment, wherein Q and R are integers, R intermediate signals phase shifted by equal degree (relative to the one with closest phase shift) in one clock period of the input signal are generated. A selection circuit may select one of the intermediate signals in one clock cycle, select the successive signals with increasing phase shift in Q clock cycles, and leave the intermediate signal with the same shift as in the previous clock cycle in the remaining ones of the M clock cycles. A counter counts a change of state in the output of the selection circuit, and generates a pulse representing an edge of the output signal at the time instance when counter counts M.

Abstract: An nth-order oscillator system for providing a resonating signal, a method of generating a resonating signal and a communications system. In one embodiment, the nth-order oscillator system, n being greater than two, includes (1) an amplifier configured to provide an intermediate signal and (2) a feedback loop including an nth-order complex LC tank and configured to generate the resonating signal by feeding back a complex-filtered form of the intermediate signal to the amplifier.

Abstract: A semiconductor device is provided comprising a main electrode (4) and a dielectric (3) in contact with the main electrode (4), the main electrode (4) comprising a material having a work function and a work function modulating element (6) for modulating the work function of the material of the main electrode (4) towards a predetermined value. The main electrode (4) furthermore comprises a diffusion preventing dopant element (5) for preventing diffusion of the work function modulating element (6) towards and/or into the dielectric (3). Methods for forming such a semiconductor device are also described.

Abstract: Methods and circuit embodiments are disclosed for implementing an improved signal path for a sample-and-hold output. In exemplary embodiments, a sample-and-hold signal path for use in a pipelined ADC includes a sample-and-hold circuit configured to operate in two distinct phases. The sample-and-hold circuit includes an input node, an output node, and a power supply node. The power supply node is configured to power down the op amp during one phase and power up the op amp during the other phase. The sample-and-hold stage is configured to provide output during one phase only. Other aspects of the invention include embodiments in which a sample-and-hold stage signal path in a pipelined analog-to-digital converter is configured to accommodate a plurality of parallel outputs.

Abstract: System and method for improving the detection performance of a wirelessly transmitted signal. A preferred embodiment comprises specifying a desired response for missed channel detection and false alarm probabilities for a plurality of signal qualities and determining if a channel detection threshold is based on missed channel detection or false alarm probabilities for the plurality of signal qualities. A signal quality estimate of a channel can be inferred from a signal quality measurement of a second channel, wherein the channel and the second channel are sourced by a single transmitter. The channel detection threshold can be adjusted based upon the previously determined required response and the signal quality estimate of the channel.

Abstract: A first-order signal generator (135). The generator comprises a shift register (210?) having a number N of bit positions. Each bit position is operable to store a binary value, the shift register operable to shift the binary value at each of the bit positions. The generator also comprises circuitry for tapping selected ones of the bit positions and circuitry for applying a function (220?) to each binary value in the selected ones of the bit positions to provide a function output. The generator also comprises circuitry for coupling the function output as an input to one of the bit positions. Lastly, the generator also comprises circuitry (230?) for outputting a first-order noise signal by coupling, as a twos complement number, each binary value in a plurality of the bit positions.

Abstract: A wireless receiver (301) for receiving multiple space time encoded signals from a plurality of transmit antenna sets (TAT1 through TAT2, and TAT3 through TAT4), wherein the multiple space time encoded signals comprise a set of symbols and wherein each transmit antenna set is coupled to a corresponding encoder (221, 222) at a single transmitter (121). The receiver comprises a plurality of receive antennas (RAT1 through RATQ) and collection circuitry (32), coupled to the plurality of receive antennas, for collecting a plurality of signal samples for a plurality of successive time instances and from each of the plurality of receive antennas. The collected samples comprise samples of multipaths of the space time encoded signals. The receiver also comprises circuitry (34, 36), coupled to the plurality of receive antennas, for determining a linear time invariant multiple-input multiple-output matrix in response to pilot values in the received multiple space time encoded signals.

Abstract: The present invention provides a method for implanting charged particles in a substrate and a method for manufacturing an integrated circuit. The method for implanting charged particles in a substrate, among other steps, includes projecting a beam of charged particles (320) to a substrate (330), the beam of charged particles (320) having a given beam divergence, and forming a diverged beam of charged particles (360) by subjecting the beam of charged particles (320) to an energy field (350), thereby causing the beam of charged particles (320) to have a larger beam divergence. The method then desires implanting the diverged beam of charged particles (360) into the substrate (330).

Abstract: A static random-access memory (SRAM) device and a method of operating the same. In one embodiment, the SRAM device includes: (1) a row of SRAM cells coupled to a word line and a power source configured to vary in voltage to enable the row of SRAM cells to operate in a retain-till-accessed (RTA) mode and (2) a word line driver coupled to the power source and configured to drive the word line.

Abstract: A bootstrapped circuit for sampling inputs with a signal range greater than supply voltage includes: a bootstrapped switch coupled between an input node and an output node; a first transistor coupled to a control node of the bootstrapped switch; a first capacitor having a first end coupled to the first transistor; a second transistor coupled between the first transistor and a supply node, and having a control node coupled to a first clock signal node; a third transistor coupled between the first transistor and the supply node; a charge pump having an output coupled to a control node of the third transistor; a level shifter coupled to a second end of the first capacitor; a fourth transistor coupled between the supply node and a control node of the first transistor; and a fifth transistor coupled between the control node of the fourth transistor and the output of the charge pump and, having a control node coupled to the supply node; wherein the second end of the first capacitor can be charged to an input voltag

Abstract: A method of fabricating an SRAM cell with reduced leakage is disclosed. The method comprises fabricating asymmetrical transistors in the SRAM cell. The transistors are asymmetrical in a manner that reduces the drain leakage current of the transistors. The fabrication of asymmetrical pass transistors comprises forming a dielectric region on a surface of a substrate having a first conductivity type. A gate region having a length and a width is formed on the dielectric region. Source and drain extension regions having a second conductivity type are formed in the substrate on opposite sides of the gate region. A first pocket impurity region having a first concentration and the first conductivity type is formed adjacent the source. A second pocket impurity region having a second concentration and the first conductivity type may be formed adjacent the drain. If formed, the second concentration is smaller than the first concentration, reducing the gate induced drain leakage current.

Abstract: A system and method for the modulation of light propagating along an optical path, for example the optical path in a projection display system. As light in the optical path travels from a light source to a display screen, it is shaped and modulated by the various components of the optical path so that the intended visual image appears on the display screen. In accordance with the present invention, a mirror disposed proximate the optical path is operable to be selectively inserted and removed from the optical path to alternately direct the light from one portion of the optical path to another, or to a light dump where it can be absorbed such that the associated heat energy may be properly dissipated. In a preferred embodiment, the mirror is a fold mirror mounted at a stop of the system to fold the light beam approximately 90 degrees when the mirror is inserted in the optical path.

Abstract: Automatic vision system object indexing and image database query system using both path-dependent and path-independent features of moving objects within a sequence of images. Feature vectors of both average over frames of an object traversing the field of view plus average over blocks of a grid for a path association. Color histograms may be an included feature.

Abstract: An overflow problem of LSF quantization in G.729 Annex B speech encoding which may lead to non-assignment of a codebook index. Preferred embodiments fix the problem with default or limited random variable assignments or flagging the overflow and adjusting the frame encoding such as by limiting spectral components or changing quantization targets.

Abstract: A method of preventing contact noise in a SiCr thin film resistor includes performing in situ depositions of a SiCr layer and then a TiW layer on a substrate without breaking a vacuum between the depositions, to prevent formation of any discontinuous oxide between the SiCr layer and the TiW layer. The SiCr and TiW layers are patterned to form a predetermined SiCr thin film resistor pattern and a TiW resistor contact pattern on the SiCr thin film resistor, and a metallization layer is provided to contact the TiW forming the resistor contact pattern.

Abstract: A cache architecture (16) for use in a processing device includes a RAM set cache for caching a contiguous block of main memory (20). The RAM set cache can be used in conjunction with other cache types, such as a set associative cache or a direct mapped cache. A register (32) defines a starting address for the contiguous block of main memory (20). The data array (38) associated with the RAM set may be filled on a line-by-line basis, as lines are requested by the processing core, or on a set-fill basis which fills the data array (38) when the starting address is loaded into the register (32). As addresses are received from the processing core, hit/miss logic (46) the starting address register (32), a global valid bit (34), line valid bits (37) and control bits (24, 26) are used to determine whether the data is present in the RAM set or whether the data must be loaded from main memory (20).

Abstract: A set of memory cell test structures and a method for assessing of the static noise margin (SNM) of a memory cell or cells, using discrete point measurement structures provided either on-chip or within the scribe lines. A set of memory structures may comprise first and second test structures, individually comprising a memory cell, having one or more left and right half-bit test structures having hard-wired connections between select nodes of each memory cell half-bit and one or more voltage supplies. The half-bits of the first test structure are configured for measuring respective left and right standby SNM values, and the half-bits of the second test structure are configured for measuring respective left and right cell ratio values at respective output nodes of the structures, using applied supply voltages for on-chip assessment of the static noise margin of the memory cells.