Abstract: A GNSS receiver includes at least one buffer and at least one correlator block. The at least one buffer stores a plurality of samples corresponding to a received signal. The at least one correlator block includes a Doppler derotation block configured to perform Doppler derotation corresponding to at least one Doppler frequency on the plurality of samples, a register array configured to be loaded with the plurality of samples on Doppler derotation corresponding to a Doppler frequency of the at least one Doppler frequency, and a correlator engine configured to generate correlation results by correlating the plurality of samples in the register array with a plurality of code phases for at least one GNSS satellite. A presence of at least one GNSS satellite signal may be detected based on coherent accumulation and a non-coherent accumulation of the correlation results.

Abstract: A wireless transmission system included at least one user equipment and a base station. The base station is operable to form a downlink control information block, modulate the downlink control information, precode the modulated downlink control information, and transmit the precoded, modulated downlink control information on at least one demodulation reference signal antenna port to the at least one user equipment. The precoded, modulated downlink control information is mapped to a set of N1 physical resource block pairs in a subframe from an orthogonal frequency division multiplexing symbol T1 to and orthogonal frequency division multiplexing symbol T2.

Abstract: An input/output (IO) circuit powered by an input/output (IO) supply voltage. The IO circuit includes a supply detector cell that detects a core supply voltage and generates a supply detect signal. A driver circuit is connected to a PAD and the driver circuit receives the supply detect signal. A failsafe circuit receives a PAD voltage. The failsafe circuit and the supply detector cell controls a leakage current from the PAD based on the IO supply voltage and the PAD voltage.

Abstract: The duration of receiver on-times may be minimized by sensing and reacting to communication channel power levels at intervals. When no energy is detected on the communication channel, then the receiver may be turned off for a channel sampling interval. If energy is detected on the channel, then the receiver may remain on to determine if a received message is associated with the device. Receiver on-time may also be minimized by adjusting the timing of messages used for broadcast messages sent by routing or other protocols. Broadcast messages, such as network routing topology messages, may be controlled in two phases. In a first phase, the broadcast messages are sent with at a high rate to allow nodes to join the network rapidly. In a second phase, the broadcast messages are sent with at a lower rate to minimize interference with data and other messages in the network.

Abstract: A multi-channel flow sensing system typically includes first and second flow-sensing transducers arranged in each channel. A data acquisition system is coupled to the first and second transducers of each of the channels. The data acquisition system is arranged to transmit and/or receive a sensing signal from at least one of the first and second transducers of each of the channels. The received sensing signals are sequentially converted and accumulated as data for billing in accordance with the measured flow within each channel. Using common components within the data acquisition system for measuring the various channels reduces costs and increases affordability in cost-sensitive areas.

Abstract: An embodiment of the invention discloses a method for testing a memory cell in an SRAM. The number of dummy memory cells on a single dummy word line used to drive the dummy bit lines is selected. A binary logical value is written to a memory cell in the SRAM. The single dummy word line and a word line containing the memory cell in the SRAM are driven to logical high values concurrently. A dummy bit line, driven by the dummy memory cells, drives an input of a buffer to a binary logical value stored in the dummy memory cells. An output of the buffer enables a sense amp to amplify a voltage developed across the bit lines electrically connected to the memory cell.

Abstract: A transmitter used in a communication system includes a raised cosine filter for transmit pulse shaping. A receiver in the communication system, designed to receive and demodulate transmissions from the transmitter, includes a root-raised cosine filter for receive pulse shaping. The use of a raised cosine filter in the transmitter enables reduction of peak-to-average ratio (PAR) of the output of a power amplifier used in the transmitter, enabling the power amplifier to be implemented to have relatively higher power efficiency than otherwise. In an embodiment, the transmitter and receiver employ ?/2-shift binary phase-shift keying (?/2 BPSK), and the raised cosine filter in the transmitter is implemented to have a roll-off factor of 0.5 and a total length of four symbol periods. In an embodiment, the root-raised cosine filter is implemented to have a roll-of factor of 0.2 and a length of four symbol periods.

Abstract: Embodiments and methods herein operate as two-stage voltage controlled current sources (i.e., dynamic current sources) operating in class AB mode. Phase-delayed current injection circuits are associated with first-stage bias, second-stage bias, or both. The current injection circuits operate to quickly re-charge inter-stage parasitic capacitance associated with the active side of the class AB dynamic current source shortly after that side becomes inactive. Doing so quickly dissipates an otherwise slowly-decaying residual drive signal to prevent the output stage from continuing to conduct after the associated side of the current source becomes inactive. Excessive current consumption and possible destructive operation of the output stage are mitigated as a result.

Abstract: A tire pressure sensor has an RFID (radio frequency identification) device having a parallel resonant circuit including an inductor and a first capacitor for generating a first radio frequency (RF) signal for transmission to a reader circuit, and a second capacitor coupled across the parallel resonant circuit by a first switch in a first position and generating a second RF signal for transmission to the reader circuit. A capacitive pressure sensor is coupled across the parallel resonant circuit by the first switch in a second position for generating a third frequency RF signal for transmission to the reader, wherein a difference in frequency between the first and third RF signals is indicative of a pressure of a tire.

Abstract: The present invention provides a method for driving a three-phase motor with a driver. The driver can provide a pulse-width modulated driving signal and a linear driving signal. The three-phase motor has a first leg, a second leg and a third leg. The method includes: connecting the second leg to the driver; floating the third leg; driving the second leg with the pulse-width-modulated driving signal from the driver; estimating a time when a voltage in the third leg will reach a predetermined threshold; and driving the second leg with the linear driving signal during that time.

Abstract: A test controller applies test stimulus signals to the input pads of plural die on a wafer in parallel. The test controller also applies encoded test response signals to the output pads of the plural die in parallel. The encoded test response signals are decoded on the die and compared to core test response signals produced from applying the test stimulus signals to core circuits on the die. The comparison produces pass/fail signals that are loaded in to scan cells of an IEEE 1149.1 scan path. The pass/fail signals then may be scanned out of the die to determine the results of the test.

Abstract: The disclosure describes a novel method and apparatus for providing expected data, mask data, and control signals to scan test architectures within a device using the falling edge of a test/scan clock. The signals are provided on device leads that are also used to provide signals to scan test architectures using the rising edge of the test/scan clock. According to the disclosure, device test leads serve to input different test signals on the rising and falling edge of the test/scan clock which reduces the number of interconnects between a tester and the device under test.

Abstract: For delivery of a chemical to a target region of a subject's brain, an apparatus comprising a storage medium on which is stored digital representations of subject-specific selective visual stimuli that, when viewed, selectively stimulate blood flow to the target area of the brain; and an electronic display device coupled thereto and configured for converting the stored digital representations to images viewable by the subject; wherein the one or more selective visual stimuli were determined by exposing the subject to a plurality of potential stimuli; measuring the blood flow response to multiple regions of the brain, including the target area and one or more non-target areas; comparing the blood flow responses to the potential stimuli, and selecting as selective stimuli potential stimuli that result in relatively more blood flow to the target area and relatively less blood flow one or more non-target areas.

Abstract: A CMOS IC containing a quantum well electro-optical device (QWEOD) is disclosed. The QWEOD is formed in an NMOS transistor structure with a p-type drain region. The NLDD region abutting the p-type drain region forms a quantum well. The QWEOD may be fabricated with 65 nm technology node processes to have lateral dimensions less than 15 nm, enabling possible energy level separations above 50 meV. The quantum well electro-optical device may be operated in a negative conductance mode, in a photon emission mode or in a photo detection mode.

Abstract: A method is provided. A communication is received by an input pin of an IC over a single-wire bus, where the communication includes a command byte. If the command byte is an initialization command byte, a self-addressing operation is performed to identify a bus address for the IC. Alternatively, if the command byte is a data movement command byte, a data movement operation is performed. When data movement operation is performed, the bus interface of the IC is set from the transparent mode to the operational mode if an operation address from the command byte matches the bus address so that a register identified in the command byte can be accessed and data movement with the register can be performed.

Abstract: The present invention employs system and method in for distinguishing between power capabilities of various external power sources and a system that can communicate the identified power capabilities to the secondary side of the wireless power transfer system. Once the secondary side of the wireless power transfer system receives the power capability information, it adjusts the current available for a payload in accordance with the information received on power source capabilities.

Abstract: A memory configurable to be used in an RTA mode includes an input latch configured to receive an input address bus and to generate a latched address bus that corresponds to a memory location. An address flop is configured to save the latched address and to generate a flopped address. A first block address pre-decoder stage is configured to generate a pre-decoded latched address to an RTA generation logic in response to the latched address bus; and a second block address pre-decoder configured to generate a pre-decoded flopped address to the RTA generation logic in response to the flopped address. The RTA generation logic generates an RTA enable signal one clock cycle before a memory block access, to activate a memory block corresponding to the memory location, such that an array supply voltage of the memory block starts charging one clock cycle before a memory block access.

Abstract: A memory system includes a memory and a memory controller coupled to the memory. The memory controller includes a data buffer configured to store a full data word as a result of a partial write operation, wherein for a subsequent partial write operation, data is read from the data buffer.

Abstract: Embodiments of methods and systems for overlapping priority contention windows in G3-PLC networks are presented. In one embodiment, a Normal Priority Contention Window (NPCW) is allowed to overlap with a High Priority Contention Window (HPCW). The minimum contention window for the normal priority frames (i.e., NPCW) is equal to or longer than the contention window for high priority frames (i.e., HPCW). By making the NPCW longer than the HPCW, the high priority frames will have a better chance than normal priority frames to get access to the channel on transmission reattempts.

Abstract: Disk drive pre-amplifier output stage circuitry is presented including a high pass input filter for removing DC offsets from differential read data signals and providing an input to AB drivers of the output stage, in which an offset test circuit selectively drives the high pass filter output nodes according to the offset at the filter input to facilitate measurement of the preceding circuit offset at the driver output terminals, and a common mode regulator circuit regulates common mode voltages at the first and second driver output nodes to a predetermined value in read and write modes.