Abstract: A method and system for ordering a priority for a function to receive any type of processing resources in a system that includes a plurality of functions. The invention includes identifying a plurality of instances of the functions that use processing resources. The invention then determines an importance of at least one of said instances by using fuzzy logic in a fuzzy inference system.

Abstract: A method that allows a digital communications system to detect the presence of transmitted messages in noisy environments. The system includes an OFDM transmitter and an OFDM receiver. The OFDM transmitter converts a digital signal to be transmitted to a plurality of sub-signals, each corresponding to a respective sub-carrier frequency. The signal is a packet including a preamble field having a known data pattern. The transmitter pre-codes the preamble data pattern, maps the data to corresponding phase information, converts the sub-signals to the time domain, and converts the sub-signals to analog form for subsequent transmission. The OFDM receiver receives the transmitted sub-signals, converts the sub-signals to digital form, converts the sub-signals to the frequency domain, and subjects the sub-signals to preamble detection processing to detect the signals' presence.

Abstract: Various systems and methods for clock management. As one example, a system for clock management is disclosed that includes a controllable oscillator, an oscillation control source, and a sample and hold circuit. The sample and hold circuit is disposed between the oscillation control source and the controllable oscillator, and is operable to introduce a transfer function having a sin x/x characteristic with a null at a switch frequency applied to the sample and hold circuit.

Abstract: The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively form high-k dielectric layers within NMOS regions. An oxide layer is formed in core and I/O regions of a semiconductor device (506). The oxide layer is removed (508) from the core region of the device. A high-k dielectric layer is formed (510) over the core and I/O regions. Then, the high-k dielectric layer is removed (512) from PMOS regions of the core and I/O regions. A silicon nitride layer is grown (516) within PMOS regions of the core and I/O regions by a low temperature thermal process. Subsequently, an oxidation process is performed (518) that oxidizes the silicon nitride into silicon oxynitride.

Abstract: Systems and methods for encoding and decoding video image data are included. In some cases, the methods are tailored for highly parallel operation on a very long instruction word processor. Various of the embodiments may be implemented in relation to H.264/MPEG-4 AVC video compression standard.

Abstract: The present invention provides a method for verifying interconnected blocks in a top-block by creating one or more assertions for each input/output of one or more blocks to be used within the top-block, creating one or more assertions for each input/output of the top-block, providing a stimulus intended to cause each assertion to be triggered, and verifying that a result for each assertion was correct. The assertions verify that a valid functional mode caused a change in an output or a valid functional mode received the change in an input. A computer program embodied on a computer readable medium can implement the foregoing steps as one or more code segments.

Abstract: A power equalization circuit in a transformer-based device having a plurality of isolated voltage outputs is provided. The circuit comprises: a threshold detection circuit configured to receive an error signal derived from a selected voltage at one of the isolated voltage outputs, and to determine whether the selected voltage is above a voltage threshold based on the error signal; a timer circuit configured to activate a wait signal after a maximum voltage drift time has expired since the selected voltage rose above the voltage threshold, and to activate a wink signal coincident with the wait signal; an overdrive current source configured to drive an error current to an overdriven value in response to the wait signal; and a commutator circuit connected to a transistor winding associated with the selected isolated voltage output, the commutator being configured to connect a transformer secondary winding to ground in response to the wink signal.

Abstract: The present invention provides a method for manufacturing a semiconductor device. The method for manufacturing the semiconductor device includes, among other steps, forming a gate structure over a substrate, the gate structure having source/drain regions proximate thereto and in, on or over the substrate, forming a pre-metal dielectric layer over the gate structure and source/drain regions, and subjecting the pre-metal dielectric layer to an energy beam treatment, the energy beam treatment configured to change a stress of the pre-metal dielectric layer, and thus change a stress in the substrate therebelow.

Abstract: In one embodiment, a method of manufacturing an integrated circuit that comprises forming a circuit layer over a substrate, forming a resist layer on the circuit layer, and subjecting the resist layer to a rework process that includes exposing the resist layer to an organic wash. In another embodiment, the method of manufacturing an integrated circuit comprises forming a circuit layer over a substrate, forming a priming layer on the circuit layer, and subjecting the resist layer to the rework process. The reworking process includes exposing the substrate to a mild plasma ash to substantially remove portions of the resist layer but leave the priming layer.

Abstract: The present invention provides a method for manufacturing a semiconductor device. The method for manufacturing the semiconductor device, among other steps, may include forming a gate structure over a substrate, forming at least a portion of gate sidewall spacers proximate sidewalls of the gate structure, and subjecting the at least a portion of the gate sidewall spacers to an energy beam treatment, the energy beam treatment configured to change a stress of the at least a portion of the gate sidewall spacers, and thus change a stress in the substrate therebelow.

Abstract: System and method for reducing failures due to hinge memory in a microdisplay display system. A preferred embodiment includes setting the state of each micromirror in a digital micromirror device based on an image being displayed, recording a usage history for the micromirrors, and providing a sequence of states to each micromirror when the display system is in an inactive mode. The sequence of states provided to a micromirror is based on the micromirror's usage history. The operation of the micromirrors while a display system containing the digital micromirror device is not in active use can help to reverse or eliminate hinge memory, thereby extending the lifetime of the digital micromirror device.

Abstract: The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the semiconductor device. The semiconductor device (100), among other possible elements, includes a gate oxide (140) located over a substrate (110), and a silicided gate electrode (150) located over the gate oxide (140), wherein the silicided gate electrode (150) includes a first metal and a second metal.

Abstract: A memory circuit and method to reduce wordline coupling is disclosed. The circuit includes a plurality of memory cells arranged in rows (702, 704, and 706) and columns (750, 752). A first conductor (710, 850) is coupled to a plurality of the rows (702, 704, and 706) of memory cells. A first transistor (810) has a current path coupled between a voltage supply terminal (800) and the first conductor (850) and a control terminal coupled to receive a first control signal (PLV). A second transistor (820) has a current path coupled between the voltage supply terminal and the first conductor and a control terminal coupled to receive a second control signal (PLW).

Abstract: A junction field effect transistor (JFET) is fashioned where a channel of transistor is buried deeply within the workpiece within which the JFET is formed. Burying the channel below the surface of the workpiece and/or away from overlying conductive materials distances a current that flows in the channel from outside influences, such as the effects of the overlying conductive materials. The deep channel also provides a more regular path for the current flowing therein by moving the channel away from non-uniformities on or near the surface of the workpiece, where said non-uniformities or irregularities would interrupt or otherwise disturb current flowing in a channel that is not as deep. These aspects of the deep channel serve to reduce noise and allow the transistor to operate in a more repeatable and predictable manner, among other things.

Abstract: A semiconductor dual guardring arrangement is provided which is useful during electrostatic discharge (ESD) events as well as during normal operating conditions. In particular, an inner guard that is located closer to an active area provides desirable performance during normal operating conditions, while an outer guardring located further from the active area provides desirable performance during an ESD event.

Abstract: A dual port memory implemented using a single port memory core. In an embodiment, the access requests from the two ports are processed in a single memory clock cycle. In one implementation, the access request corresponding to the first port is processed in the high logic state of the memory clock cycle, and the access request corresponding to the second port is processed in the low logic state of the memory clock cycle. A single port memory core may provide multiple memory enable signals and corresponding strobe signals, with each combination of memory enable signal and strobe signal facilitating the memory access request from a corresponding port. An alternative embodiment uses the duration of each clock cycle of the memory clock signal more efficiently by starting the second memory access soon after completion of the first memory access (without waiting for the logic low of memory clock signal).

Abstract: An integrated circuit includes a composite transistor including at least a first transistor of a first technology type having a first group of intrinsic properties and a second transistor of a second technology type having a second group of the intrinsic properties, at least one of the intrinsic properties of the second group being substantially different than a corresponding intrinsic property of the first group, the second transistor having a first electrode coupled to a supply voltage, a second electrode coupled to a first electrode of the first transistor, and a control electrode coupled to a bias voltage conductor and also coupled to a control electrode and a second electrode of the first transistor. A source of bias current is coupled to the bias voltage conductor and is also coupled to the second electrode of the second transistor. A bias voltage across the composite transistor is produced on the bias voltage conductor to bias a cascode transistor of the first technology type.

Abstract: A system and method facilitate estimating noise in a received signal. The received signal is formed of a plurality of tones, such as training tones and data tones. Noise is estimated at the training tones, which generally comprise a lesser number of the tones in the received signal than the data tones. The estimated noise at the training tones can be employed to facilitate demodulating and/or decoding data tones in the received signal. In one aspect, the estimated training tone noise can be utilized by a beamformer.

Abstract: Systems and methods are provided for correcting color phase error in a video decoder system. A demodulator system demodulates the composite input signal and the at least one delayed signal to produce sets of baseband chroma components based on a phase correction value. Color phase correction logic determines the phase correction value for the demodulator system based upon characteristics of the baseband chroma components associated with a series of at least two consecutive frames.

Abstract: The creation, modification, and deletion of a traffic stream 224 with parameterized QoS expectations between two communicating stations 205 and 207, when there is no built-in mechanism for support of parameterized QoS expectations, requires signaling of traffic characteristics and QoS parameters between the management entities such as SME 212 and MLME 214 and between the MAC entities of the communicating stations 205 and 207. Either the station 205 and 207 or a hybrid coordinator may initiate the signaling. The end result of the signaling is the creation of a new traffic stream that is used to associate user traffic to a particular set of traffic characteristics and QoS parameters, which are then used in the scheduling of the transmission of the user traffic. Another end result of the signaling is the modification of an existing traffic stream in terms of its traffic characteristics and QoS parameters.