Abstract: The creation, modification, and deletion of a traffic stream 224 with parameterized QoS expectations between two communicating stations 205 and 207, when there is no built-in mechanism for support of parameterized QoS expectations, requires signaling of traffic characteristics and QoS parameters between the management entities such as SME 212 and MLME 214 and between the MAC entities of the communicating stations 205 and 207. Either the station 205 and 207 or a hybrid coordinator may initiate the signaling. The end result of the signaling is the creation of a new traffic stream that is used to associate user traffic to a particular set of traffic characteristics and QoS parameters, which are then used in the scheduling of the transmission of the user traffic. Another end result of the signaling is the modification of an existing traffic stream in terms of its traffic characteristics and QoS parameters.

Abstract: A data synchronization arrangement is provided for exchanging clocked data between different clock domains running at the same clock frequency but at an arbitrary relative phase shift. An input data stream synchronized in the first clock domain is written into respective locations of a buffer memory through a write select multiplexer under control of a write select shift register clocked by the first domain clock. An output data stream synchronized in the second clock domain is read from the respective locations of the buffer memory through a real select multiplexer under control of a read select shift register clocked by the second domain clock. A bit synchronization circuit is provided for loading the read select shift register with a bit pattern that has a relative offset relative to the bit pattern of the write select shift register, to correlate for the difference in clock phases.

Abstract: In accordance with the invention there is a method of forming a semiconductor device comprising forming a gate over a substrate, forming a source region and a drain region by doping a first portion and a second portion of active regions adjacent the gate, and forming a first recess in a portion of the source region and a second recess in a portion of the drain region. The method also includes activating the dopants in the source region and the drain region by heating the active regions and depositing a semiconductor material in the first recess and the second recess after activating the dopants in the source region and the drain region.

Abstract: An integrated circuit device (100) includes circuitry for providing a first shift argument (L[4:0]) indicating shift positions in a first direction and circuitry for providing a second shift argument (R[4:0]) indicating shift positions in a second direction. One rotate stage (ROTATE STAGE 1), in a plurality of rotate stages, is coupled to receive the initial data argument. Each rotate stage, other than the one rotate stage, is coupled to receive a data argument from an output of another one of the rotate stages. Further, each rotate stage is operable to rotate the data argument input into the corresponding rotate stage in response to less than all bits of at least one of the first and second shift arguments. At least one rotate stage is operable to rotate the data argument input into the corresponding rotate stage in response to a sum of respective bit positions of the first and second shift arguments.

Abstract: To oscillate and output multiphased triangular waves with a designed waveform shape, wave crest value, and phase relationship. This multiphased triangular wave oscillating circuit has two triangular wave generating circuits 10A and 10B for generating two phased triangular waves A and B with phases opposite each other, a middle point potential fixing element 20 that always fixes the middle point potential of the output voltage A and B of the two triangular wave generating circuits 10A and 10B at a fixed value, and a mode switching element 30 that instantly switches the output voltage generation mode (up-slope waveform mode/down-slope waveform mode) in the two triangular wave generating circuits 10A and 10B at a preset reference wave crest value level.

Abstract: A filter includes a tap multiplication circuit and a tap digital-to-analog (“DAC”) unit coupled to the tap multiplication circuit. Further, a plurality of clocks are provided that control timing associated with the tap multiplication circuit and that permit one tap multiplication to be output while another tap multiplication is being computed for a 1/N rate implementation.

Abstract: Hardware cells inside of an IC device, such as in a processor circuit, for characterization that replace functional flip-flops that capture inputs or drive outputs in the device. The cells are circuits that are used, in conjunction with a software method, to generate test programs for testing exact I/O transitions for timing measurements at various operating conditions.

Abstract: An architecture for a cascaded digital filters comprises independently programmable controlling registers and independent interpolating factors; a digital to analog converter for converting the digital signals into analog signals with a constant sampling rate which matches with the interpolating factors of the cascaded digital filters. Each filter property (filters order, coefficient symmetry, half-band, and poly-phase) can be programmed independently to support different system requirements and extract maximum throuput from a given hardware. The method of filtering digital signals comprises the steps of determining an interpolation factor of the cascaded digital filters with the lowest number of computations so as to match with the single sampling rate of the digital to analog converter, determining active filters and an interpolation factor of each digital filter in the cascaded digital filters, and determining a mode of operation of the cascaded digital filters.

Abstract: A semiconductor device (400) with a plastic package (401) having on its surface (401a) a mark (402) identifying the location, where the runner for the molding compound was broken off. The device further exhibits a leadframe with a pad, which has a planar area (403) and a tab (404). The tab is bent at an angle (405) between 120° and 160°, preferably about 135°, towards the planar area and reaches a height (406) over the area. At least portions of the leadframe, including the pad and the tab, are encapsulated by the package; the tab (404) is parallel to the package side (401a) with the mark (402). The device has a semiconductor chip (410) attached to the pad; the thickness (411) of the chip is between 0.5 times and 1.0 times, preferably about 0.7 times, the tab height over the pad.

Abstract: Determining a scan vector which would test an integrated circuit (IC) while ensuring counts in respective portions of the IC would not exceed corresponding thresholds. In an embodiment, the threshold represents a number of toggles in the corresponding portion. The toggles can include the transitions that would be caused by the logical operation of the combinatorial elements in the IC as well as the transient glitches caused by arrival of input signals at different time points.

Abstract: A file system which ensures that some of the (desired) files (“linear files”) are stored in corresponding exclusive blocks (i.e., a block that stores data corresponding to one file only). Due to such a feature, rewriting of data corresponding to other files would not cause data corresponding to linear files to be relocated/rewritten. Such a feature may provide reliable and steady retrieval of data of the corresponding file from a flash memory organized as sectors. According to another aspect, some of the files (“non-linear files”) are stored in non-exclusive blocks (i.e., multiple files can share the same block or the same file can span multiple blocks without contiguity).

Abstract: An IC includes an IEEE 1149.1 standard test access port (TAP) interface and an additional Off-Chip TAP interface. The Off-Chip TAP interface connects to the TAP of another IC. The Off Chip TAP interface can be selected by a TAP Linking Module on the IC.

Abstract: A system and method for wireless local area network throughput enhancement includes an access point and an endpoint station in a wireless computer network transmitting data packets over radio frequency signals, and reordering the data packets into a megapacket in the access point using concatenation of the data packets. The method provides a significant throughput enhancement on wireless networks including IEEE 802.11 networks.

Abstract: Estimation of gain and phase imbalance of an upconverting transmitter. A transmitter transmits symbols containing vector components of pre-specific relationship in an analog signal. A receiver (also contained in a transceiver along with the transmitter) examines the symbols to determine the phase and gain imbalances in the transmitter based on the analog signal. An aspect of the present invention enables the balance estimation circuit to be integrated along with the transmitter and the receiver into a single monolithic integrated circuit.

Abstract: Methods are disclosed for forming ultra shallow junctions in semiconductor substrates using multiple ion implantation steps. The ion implantation steps include implantation of at least one electronically-active dopant as well as the implantation of at least two species effective at limiting junction broadening by channeling during dopant implantation and/or by thermal diffusion. Following dopant implantation, the electronically-active dopant is activated by thermal processing.

Abstract: Asynchronous sampling rate converter with input/output frequency ratio estimation and polyphase filtering uses FIFO level feedback to adaptively control frequency ratio estimation.

Abstract: In order to reduce distortion in playout of audio received in a packet over a packet network, the playout unit needs to determine the relative delay of adjacent packets, jitter, present in the network. The jitter is used to determine buffering for smoothing playout of audio in a packet network. The jitter in packets received from a packet network is calculated based upon the arrival time of a packet, the length of the packet and the arrival time of a subsequent packet. The receiving gateway notes the arrival time of a packet. The length of the audio payload is determined from the size of the payload and the codec used to encode the payload. The length of the payload is added to the arrival time to determine the anticipated arrival of the next subsequent packet. The actual arrival time is noted and the difference between anticipated arrival and actual arrival is used to determine jitter.

Abstract: Methods fabricate DEMOS devices having varied channel lengths and substantially similar threshold voltages. A threshold voltage is selected for first and second devices. First and second well regions are formed. First and second drain extension regions are formed within the well regions. First and second back gate regions are formed within the well regions according to the selected threshold voltage. First and second gate structures are formed over the first and second well regions having varied channel lengths. A first source region is formed in the first back gate region and a first drain region is formed in the first drain extension region. A second source region is formed in the second back gate region and a second drain region is formed in the drain extension region.

Abstract: The invention provides a method and apparatus for evaluating the quality of microelectromechanical devices having deformable and deflectable members using resonation techniques. Specifically, product quality characterized in terms of uniformity of the deformable and deflectable elements is inspected with an optical resonance mapping mechanism on a wafer-level.

Abstract: An integrated circuit structure including multiple thin film resistors having different sheet resistances and TCRs includes a first oxide layer (2) formed on a semiconductor substrate (1), a first thin film resistor (3) disposed on the first oxide layer (2), and a second oxide layer (14) disposed over the first oxide layer (2) and first thin film resistor (3). A second thin film resistor (15) is formed on the second oxide layer (14) and a third oxide layer (16) is formed over the second thin film resistor (15) and the second oxide layer (14). Interconnect metallization elements (12A,B & 22A,B) disposed on at least one of the second (14) and third (16) oxide layers electrically contact the circuit element (4), terminals of the first thin film resistor (3), and terminals of the second thin film resistor (15), respectively, through corresponding contact openings through at least one of the second (14) and third (16) oxide layers.