Abstract: A circuit comprising a channel encoder circuit coupled to receive an input data sequence and produce an output data sequence. An interleaver circuit coupled to receive the output data sequence and produce an interleaved data sequence. An encoder circuit coupled to receive the interleaved sequence and produce a first encoded symbol at a first output terminal at a first time and produce a first transform of a second encoded symbol at a second output terminal at the first time and produce the second encoded symbol at the first output terminal at a second time and produce a second transform of the first encoded symbol at the second output terminal at the second time.

Abstract: A method of operating a computing system to determine reticle data. The reticle data is for completing a reticle for use in projecting an image to a semiconductor wafer. The method receives circuit design layer data comprising a desired circuit layer layout, and the layout comprises a plurality of lines. The method also identifies in the plurality of lines a first line portion for use as a first circuit function and a second line portion for use as a second circuit function that differs from the first circuit function. The first line portion is parallel and adjacent to the second line portion. The method also provides the reticle data in an output data file for use in forming features on the reticle.

Abstract: The present invention defines a system (100) for detecting copper contamination within a semiconductor manufacturing process. According to the present invention, a semiconductor wafer (102) is transferred (108) from a semiconductor manufacturing component (104), which may have exposed the wafer to copper contamination, to a measurement system (106). The measurement system measures an electrical value at a plurality of locations along a surface of the wafer, prior to and after exposure of the surface to an activation system (112). The activation system is provided to cause any copper contamination along the surface to form a precipitate thereon. An analysis component (110) is provided to receive electrical value and location information from the measurement system and to identify, from the measurements, the presence and location of copper contamination along the semiconductor wafer surface.

Abstract: Systems and methods are disclosed to for detecting movement of an object. In one embodiment, a system is disclosed to detect movement of an object (e.g., a tire). The system includes a sensor that is operative to sense at least a pressure condition within an enclosed space of the object based on an operating mode of the system. A control system controls the operating mode of the system based at least in part on whether movement of the object is detected. The movement of the object is detected based on a variation in the at least a pressure condition over time. The system can be implemented as part of a tire pressure monitoring system.

Abstract: Maintaining synchronization when sending/receiving multiple channels of data with a corresponding common reference clock signal. Synchronization signals (e.g., pulses) are generated periodically and the timing of channels is adjusted. In an embodiment, multiple sequences of parallel data elements are received on corresponding parallel data channels using a first common clock signal. Each sequence of parallel data elements is converted to a corresponding sequence of serial data elements. The serial data elements are transmitted on a corresponding serial channel using a serial clock as a common reference. A synchronization signal may be generated periodically with a time period of (the number of bits in each parallel data element x the time period of the serial clock), wherein ‘x’ represents multiplication operation. As the parallel data channels are synchronized in short intervals, synchronization is maintained.

Abstract: Reducing the effect of coupling on a reference voltage received at a node of an output buffer, wherein the effect of coupling is due to the transitions in the output signals. An inverted signal of the output signal is connected to the node through an impedance (e.g., capacitor) that stores energy. The inverted signal pulls the node in the opposite voltage level direction compared to the coupling effect of the output signal, thereby leaving the reference voltage substantially unchanged. By selecting the capacitance of the capacitor equaling the parasitic capacitance between the node and the output of the output buffer, coupling may be reduced substantially.

Abstract: A self-clocking memory device comprises a memory array, a memory input circuit, and a memory control circuit. The memory input circuit is operable to receive an input clock signal and generate a memory operation initiation signal in response thereto, while the memory control circuit is operable to receive the memory operation initiation signal and generate one or more control signals to initiate a memory operation in response thereto. The memory control circuit is further operable to identify completion of the memory operation and generate a cycle ready strobe signal in response thereto. The memory input circuit receives the cycle ready strobe signal as an input and generates a next memory operation initiation signal in response thereto for initiation of a next memory operation.

Abstract: Reference generator systems (108, 130) and methods (200) are presented for providing bitline reference voltages for memory access operations in a ferroelectric memory device (102). The reference generator system (108, 130) comprises a primary capacitance (130), a precharge system (132) that charges the primary capacitance, and a reference system (108) with a plurality of local reference circuits (108a) associated with corresponding array columns that individually comprise a staging capacitance (Cs), a first switching device (S1) coupled between the staging capacitance and the primary capacitance (130), and a second switching device (S2, S3) coupled between the staging capacitance (Cs) and a bitline of the corresponding array column.

Abstract: The object of this invention is to improve efficiency in the step-up/down mode and eliminate ringing in the output voltage when switching between the step-up mode and the step-up/down mode. This DC-DC converter has a local feedback control pre-processing circuit 12 arranged between voltage input terminal IN and one of the terminals of choke coil 10 or node Nx as well as an output feedback control booster circuit 14 arranged between the other terminal of choke coil 10 and the voltage output terminal OUT. Pre-processing circuit 12 has switching elements 16 and 18 and control circuit 20 that turns on/off switching elements 16 and 18 in a complementary manner. Control circuit 20 has error amplifier 22, reference voltage generating circuit 24, PWM comparator 26, inverter 28, and low-pass filter (LPF) 30.

Abstract: A method (100) of forming fully-depleted (90) and partially-depleted (92) silicon-on-insulator (SOI) devices on a single die in an integrated circuit device (2) is disclosed using SOI starting material (4, 6, 8) and a selective epitaxial growth process (110).

Abstract: The low AC impedance input stage circuit for fast startup applications includes: a first transistor coupled between a first input node and a first output node; a second transistor coupled between a second input node and a second output node, and having a control node coupled to a control node of the first transistor; a third transistor coupled to the first input node and having a control node coupled to the control node of the first transistor; a fourth transistor coupled to the second input node and having a control node coupled to the control node of the third transistor; a first blocking device coupled between the third transistor and a first current source; a second blocking device coupled between the fourth transistor and the first current source; and a bias device coupled between the first current source and the control node of the first transistor.

Abstract: An improved copper ECD process. After the copper seed layer (116) is formed, a first portion of copper film (118) is plated onto the surface of the seed layer (116). The surface of the first portion of the copper film (118) is then rinsed to equalize the organic adsorption on all sites to prevent preferential copper growth in dense areas. After rinsing, the remaining copper of the copper film (118) is electrochemically deposited.

Abstract: A method (1300) of forming a semiconductor device comprising an isolation structure is disclosed, and includes forming a trench region within a semiconductor body (1308). Then, surfaces of the trench region are nitrided (1310) via a nitridation process. An oxidation process is performed that combines with the nitrided surfaces (1312) to form a nitrogen containing liner. Subsequently, the trench region is filled with dielectric material (1316) and then planarized (1318) to remove excess dielectric fill material.

Abstract: A method of forming a film stack in an integrated circuit, said method comprising depositing a layer of silicon carbide adjacent a first layer of dielectric material, depositing a layer of silicon nitride adjacent the layer of silicon carbide, and depositing a second layer of dielectric material adjacent the layer of silicon nitride.

Abstract: Methods and apparatus for optimizing wireless communications channels by employing multi-channel modulation techniques in wireless communication systems is disclosed. The wireless communications channel may comprise tones, and data may be allocated differently among the different tones according to the channel characterization measurements. In one embodiment, a method may include: transmitting data over a wireless channel using a first station (e.g., an access point), receiving the data using a second station, performing calculations on the received data, and allocating subsequent data transmissions among the tones according to the calculations. Other embodiments may utilize superfluous data transmissions—for example, data coming from the access point that is intended for other stations—in order to calculate channel characterization. Preferably, any portion of the transmitted data (e.g., preamble, header, data, etc.) may be used to calculate channel characterization.

Abstract: According to one embodiment of the present invention a micro-mirror element comprises a lower layer, a first middle layer, a second middle layer, and a micro-mirror. The lower layer includes an address portion for receiving an address voltage and a bias portion for receiving a bias voltage respectively. The first middle layer is electrically coupled to the bias portion of the lower layer. The second middle layer is electrically coupled to the first middle layer. The micro-mirror is coupled to the second middle layer and comprises a reflective surface operable to selectively tilt, in response to an application of a bias voltage and an address voltage to the lower layer, to reflect a beam of light.

Abstract: The present invention facilitates semiconductor fabrication by maintaining shape and density of an etch stop layer (206) during trench fill operations. The shape and density of the etch stop layer (206) is maintained by forming a protective alloy liner layer (310) on the etch stop layer (206) prior to trench fill operations. The protective alloy liner (310) is comprised of an alloy that is resistant to materials employed in the trench fill operations. As a result, clipping and/or damage to the etch stop layer (206) is mitigated thereby facilitating a subsequent planarization process that employs the etch stop layer (206). Additionally, selection of thickness and composition (1706) of the formed protective alloy (310) yields a stress amount and type (1704) that is applied to channel regions of unformed transistor devices, ultimately providing for an improvement in channel mobility.

Abstract: The present invention provides a method of manufacturing a metal silicide electrode (100) for a semiconductor device (110). The method comprises implanting small atoms into an nMOS semiconductor substrate (130) to a depth (132) no greater than about 30 nanometers into the nMOS semiconductor substrate. The method further comprises depositing a transition metal layer (400) over the nMOS semiconductor substrate. The transition metal layer and the nMOS semiconductor substrate are reacted to form the metal silicide electrode. Other aspects of the present invention include a method of manufacturing an integrated circuit (700).

Abstract: Today many instances of IEEE 1149.1 Tap domains are included in integrated circuits (ICs). While all TAP domains may be serially connected on a scan path that is accessible external to the IC, it is generally preferred to have selectivity on which Tap domain or Tap domains are accessed. Therefore Tap domain selection circuitry may be included in ICs and placed in the scan path along with the Tap domains. Ideally, the Tap domain selection circuitry should only be present in the scan path when it is necessary to modify which Tap domains are selected in the scan path. The present invention describes a novel method and apparatus which allows the Tap domain selection circuitry to be removed from the scan path after it has been used to select Tap domains and to be replaced back into the scan path when it is necessary to select different Tap domains.

Abstract: The present invention facilitates clock and data recovery for serial data streams by selecting a clock phase for each input data transition and generating a recovered clock. In order to identify data transitions, the received serial data stream is sampled N times per ideal bit time, where the minimum value for N must be greater than 2/(1?(2*jitter_ratio)) and jitter_ratio is the fractional representation of the portion of the ideal bit time during which transitions can be expected or estimated to occur. On identifying a transition, a toggle phase is set. In order to avoid stale clock phase selection resulting from jitter and the like, one phase after the toggle phase is blocked or prevented from being selected for the clock. Finally, a clock phase is selected N/2 phases from the toggle phase and a recovered clock is generated by combining the individually selected clock phases.