Abstract: Method and apparatus for serial data transfer between at least two modules (10, 12) connected to each other by way of a serial data bus (18) where the data transfer is governed by a clock signal (CLK). The modules (10, 12) each comprise a receiver unit (30) for the reception of the data and a transmitter unit (22) for the transmission of data. The output of a data value by the transmitter unit (22) of one module (12) to another module (10) at the serial data bus (18), and the import of the data value by the receiver unit (30) of the corresponding other module (10) are initiated by slopes of the clock signal (CLK). The clock signal that triggers the transmission of this data value in the one module (12) is delayed via a delay element (38) one pulse repetition period (?TP) of the clock signal (CLK).

Abstract: An SRAM device comprising a column having opposing bit lines, asymmetric memory cells spanning the opposing bit lines in alternating orientations, and a sense amplifier. The sense amplifier includes sensing circuitry configured to sense values stored in the cells and switching circuitry configured to apply signals to the sensing circuitry as a function of the orientations.

Abstract: An architecture for a biquad (70), second-order infinite impulse response (IIR) digital filter, that is capable of operating at maximum efficiency, is disclosed. The biquad (70) includes coefficient memory (50) and data memory (52), along with control circuitry (53) that loads values from these memories (50, 52) into a coefficient register (52) and a data register (54), respectively. A multiplier (55) multiplies the values in the coefficient register (52) and data register (54), with the resulting product being stored in a product register (58). An accumulator (59) adds successive product results to derive a new output value in each instance of the IIR filter. A shadow register (60) temporarily stores the output of the accumulator (59) from a previous instance, permitting this output to be stored in the data memory (52) at a later time in the sequence.

Abstract: A system and method for exposing different parts of a single field of view for various and differing lengths of time while capturing an image is provided. For astrophotography, unwanted light pollution or over-saturation bleeding from nearby or obtrusive stars may be greatly reduced or eliminated while still capturing the image of the nearby brighter star in the same field of view. Also, a system and method for real-time contrast control while capturing an image to optimize signal-to-noise ratio for various parts of the captured image, is provided. An embodiment of the present invention provides such techniques by using spatial light modulator devices, such as a digital micro-mirror device, to controllably mask different portions of light from an image that expose film or a charge-coupled device. A system and method for a way to use a spatial light modulator device as an active and controllable mask for photolithography, is provided.

Abstract: The programmable transition state machine of this invention is designed to allow implementation of hardware capable of increasing the performance of critical encoding and decoding tasks in a microprocessor environment where a required encoding or decoding or machines is not known in advance. The state machine described may also be used in systems that need flexibility to support a wide variety of functions or machines or where a hardwired approach is not useful. This unique state machine processes the state information and the transition from a present state to a next state in CPU-programmable logic.

Abstract: An insulating layer (3) having an opening portion (3a) at a position conformable to an electrode pad (2) is formed. Next, a resin projection portion (4) is formed on the insulating layer (3). Thereafter, a resist film is formed which has opening portions made in regions conformable to the opening portion (3a), the resin projection portion (4) and the region sandwiched therebetween. A Cu plating layer (6) is formed by electrolytic copper plating, using the resist film as a mask.

Abstract: A phase lock loop circuit 60 has a phase frequency detector 62, a charge pump 64, an active filter 87 and a voltage-controlled oscillator 100. The phase detector generates UP and DN signals indicative of the relative frequency of FR, a reference signal, and FV, a signal controlled by the voltage-controlled oscillator. A charge pump using logic gates (buffer 66 and inverter 68) to produce a voltage drop over resistors 74 and 84 to generate a voltage at a node coupled to the input of transmission gate 76 according to the values of the UP and DN signals. When the transmission gate 76 is closed (low impedance) the charge pump may sink or source current to the inverting input of the operational amplifier 86 of the active filter 86. When the transmission gate is open (high impedance state) the inverting input is electrically isolated from the node.

Abstract: The present invention provides a robust solution to the task of re-aligning data at the transmit end of a fiber optic or other high performance serial link, and also offers flexibility in the circuit board design approach. A high performance analog phase locked-loop circuit is used to simultaneously provide clock recovery for multiple bit streams. The power dissipation required to perform clock recovery is thereby reduced to a fraction of that required in conventional transmit systems. This analog phase locked loop produces plural phase output signals. An output multiplexer selects one phase for use in electrical to optical conversion.

Abstract: A micromirror array comprises micromirrors of different properties for use particularly in display systems. Micromirrors of different properties can be arranged within the micromirror array according to a predetermined pattern, or randomly. However, it is advantageous to arrange the micromirrors with different properties within the micromirror array neither in complete order nor complete in random.

Abstract: Electrical fuses (eFuses) are applied to the task of achieving very tightly controlled Input-Output (I/O) timing specifications. The I/O timing is made programmable and subject to adjustment as part of wafer probe testing. The techniques of parametric adjustment presented are based upon what is commonly referred to as clock skewing or clock tuning. The invention describes methods to select the clock skewing on a die-to-die basis based on functional testing with the actual parametric limits imposed on parameters of interest. The results associated with each die form the basis for hard-programming the selected clock skew value into the die via electrical fuses.

Abstract: Multi-capacitor drain extended transistor devices and methods are provided. A first capacitor structure comprises a first dielectric layer (14) and a first gate layer (16) and first and second lateral sides. The first capacitor structure overlies a channel region of a first conductivity type in a semiconductor substrate (4). A second capacitor structure comprising a second dielectric layer (26) and a second gate layer (28) is formed overlying the first gate structure. A source region (22) of a second conductivity type formed in the semiconductor substrate (6) proximate the first lateral side of the gate and a drain extension region/well (12) lightly doped of the second conductivity type is formed in the semiconductor substrate under a portion of the gate structure. A drain region (24) of the second conductivity type formed within the drain extension region (12). The first capacitor structure and the second capacitor structure connect in series to permit a higher operational gate voltage.

Abstract: Two scales having unequal pitches are used to measure lengths with a greater resolution than that offered by an image capturing system operating alone. In an embodiment, the different pitches are attained by having bands of unequal width in the two scales. Images representing the overlapping patterns of the two bands are captured in a digital format before and after a move. The bit patterns resulting from such capturing are examined to determine the length of the move with a high resolution according to Vernier principles. The length of the move can in turn be used to measure the length of an object with high resolution.

Abstract: The present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit including the semiconductor device. The method for manufacturing the semiconductor device, among other possible steps, forming a polysilicon gate electrode (250) over a substrate (210) and forming a protective layer (260) over the polysilicon gate electrode (250) to provide a capped polysilicon gate electrode (230). The method further includes forming a protective oxide (510) on a surface proximate the polysilicon gate electrode (250), and removing the protective oxide (510) using a wet etch, the wet etch not having a substantial impact on the protective layer (260).

Abstract: A switch mode power converter that limits the in-rush current at start-up and reduces the occurrence of output voltage overshoot over a range of switching frequencies. The converter includes at least one Soft-Start (SS)/Frequency-Select(FS) input, at least one oscillator enable input, and an oscillator having at least one control input. Soft-start programming is linked to the frequency selection of the converter. An external capacitor connected between the SS/FS input and ground is employed to program the soft-start time, and the switching frequency generated by the oscillator is selected via the state of the SS/FS input.

Abstract: The charge pump circuit includes: a charge pump output branch; a current leakage device coupled to the output branch; and a feedback device coupled between the output branch and a control node of the current leakage device such that the leakage device cancels leakage current from the output branch.

Abstract: Servo error signal circuitry apparatus and methods are described. The difference between two bottom envelope signals SEbtm and SFbtm is calculated by a subtracter (40) to generate a difference signal (SEbtm?SFbtm). The difference signal (SEbtm?SFbtm) is input as an alignment signal (AL) to an equalizer (42) and as a basic tracking error signal to the positive input terminal of a second subtracter (52). On the other hand, the difference between two top envelope signals SEtop and SFtop is calculated by a third subtracter (48) to generate a difference signal (SEtop?SFtop). The signal K(SEtop?SFtop) obtained by multiplying a coefficient K with the difference signal using a coefficient multiplier (50) is input to the negative input terminal of the second subtracter (52). The difference signal {(SEbtm?SFbtm)?K(SEtop?SFtop)} output from the second subtracter (52) is used as an offset corrected tracking error signal.

Abstract: System and method for correcting an inaccurate clock with the use of an accurate reference clock. A preferred embodiment comprises repeatedly counting clock cycles in a clock signal generated by the inaccurate clock for a specified period of time, after the completion of each specified period of time, computing a delta value based on the clock cycle counts of the clock signal of the inaccurate clock, accumulating a delta sum value, and computing a clock adjustment value for the inaccurate clock based upon the delta sum value. The reference clock is used to mark the end of each specified period of time.

Abstract: A method of variable length coding classifies each received symbol into one of a plurality of classifications having a corresponding variable length code table selected based upon a probability distribution of received symbols within the classification. The variable length codeword output corresponds to the received symbol according to the variable length code table corresponding to the classification of that received symbol. The plurality of classifications and the corresponding variable length code tables may be predetermined and fixed. Alternatively, the variable length code table may be dynamically determined with data transmitted from encoder to decoder specifying the variable length code tables and their configurations. Universal variable length code (UVLC) is used to code the symbols. Universal variable length code can instantiate to different variable length code tables with different parameters.

Abstract: A full-duplex transceiver using a method immunizing itself against self-jamming. The transceiver includes a receiver and a transmitter. The receiver includes a frequency immunization converter and a high pass IF filter. The transmitter transmits a TX signal. The receiver receives an RX signal and simultaneously receives a portion of the power of the TX signal as an undesired TX jamming signal. The frequency immunization converter uses the center frequency of the TX signal for downconverting the RX signal to an IF signal and simultaneously downconverting the TX jamming signal to near zero frequency. The high pass IF filter passes the IF signal and blocks the signal at near zero frequency. As a consequence of the downconversion using the TX frequency, a second LO frequency is controlled for avoiding image frequencies.

Abstract: The present invention provides a ferroelectric capacitor, a method of manufacture therefor, and a method of manufacturing a ferroelectric random access memory (FeRAM) device. The ferroelectric capacitor (100), among other elements, includes a substantially planar ferroelectric dielectric layer (165) located over a first electrode layer (160), wherein the substantially planar ferroelectric dielectric layer (165) has an average surface roughness of less than about 4 nm. The ferroelectric capacitor (100) further includes a second electrode layer (170) located over the substantially planar ferroelectric dielectric layer (165).