Abstract: A system and method of providing a micromirror pixel 400 that is highly resistant to bright failure states. The micromirror 400 uses an asymmetric yoke 402 to ensure the mirror is only attracted to the address electrode in one rotation direction. The landing mechanism on the other side of the torsion binge axis also is altered to allow the pixel to over rotate in the “off” direction. The over rotation ensures that light reflected by the mirror when in the off direction will miss the projection lens pupil, allowing the corresponding pixel to remain dark in both an operational and failed state.

Abstract: Apparatus and methods for applying solder paste to circuits, such as integrated circuits, are disclosed. The apparatus and methods comprise a squeegee blade having a pair of elongated face sides spaced apart by a selected thickness and a corresponding pair of elongated substantially parallel narrow sides spaced apart by a selected width. The elongated face sides and elongated narrow sides join together to form squeegee operating edges. The squeegee blade is free of mounting aperture as to provide four operating edges. The squeegee blade is mounted to a resilient clamping structure which applies a regular and controlled gripping force so as to avoid deformation of the squeegee blade edge due to excessive mounting force. The plurality of fasteners are received by the clamping structure for adjusting the gripping force to the squeegee blade.

Abstract: The present invention provides a solution to the dual problems of mobility and portability associated with using a portable telephone in combination with a portable computer. An interface module (40) has a first interface (44) for coupling to an interface (34) on a portable telephone (16) and a second interface (58) for coupling to an interface (68) on a portable computer (62). The interface module (40) facilitates a direct connection between a coupled interface module and portable telephone (60) to a portable computer (62). The interface module (40) electrically couples the portable telephone (16) to the portable computer (62) thus eliminating the need for a cable or tethered connection between the portable computer (62) and portable telephone (16).

Abstract: CMOS gate structure with metal gates having differing work functions by texture differences between NMOS and PMOS gates.

Abstract: Disclosed are new methods and systems for achieving calibration in a pipelined ADC system. The methods and systems may be used to provide continuous digital background calibration in a pipelined ADC. Component mismatch error from each DAC in the pipeline is tabulated to provide an integral nonlinearity profile, which is subtracted from the ADC transfer characteristic.

Abstract: An apparatus for use with a digital micro-mirror includes a hinge disposed outwardly from a substrate and capable of at least partially supporting a micro-mirror disposed outwardly from the hinge. The micro-mirror capable of being selectively transitioned between an on-state position and an off-state position based at least in part on a bias voltage received by a conductive conduit. The apparatus also includes a conductive layer disposed inwardly from the at least one micro-mirror. In one particular embodiment, the conductive layer enables a conductive path for the bias voltage substantially inwardly from a periphery of the micro-mirror.

Abstract: The present invention relates to a hard disk drive system having overvoltage protection circuits for various types of overvoltage conditions. For example, the system includes one or more hard disk drive integrated circuit chips residing on a board and a hard disk drive power plug receptacle residing on the board having two different value power supply ports associated therewith. The receptacle is operable to receive a power plug therein, wherein when the power plug is inserted therein in a proper orientation the two different value voltages are properly supplied to the one or more hard disk drive integrated circuit chips, and wherein when the power plug is inserted therein in an improper orientation the two different value voltages are switched with respect to their intended values.

Abstract: The invention provides a method and device for building one or more passive components into a chip scale package. The method includes the steps of selecting a passive component having a terminal pitch that is a multiple of the package ball pitch of a chip scale package and mounting the selected passive component terminals to ball sites of the package. A preferred embodiment of the invention uses a single metal layer polyamide tape as the substrate of the package. Additional preferred embodiments of the invention are disclosed in which the terminal pitch multiple of the package ball pitch is one or two. Devices corresponding to the disclosed methods are also disclosed.

Abstract: An electronic integrated circuit includes a signal path connected between the functional logic (15) thereof and an external output terminal thereof, which signal path includes a memory circuit (121C, 127C). The memory circuit is coupled to the output terminal and is selectively operable to detect and resolve voltage contention at the output terminal, and is also selectively operable to isolate itself from voltages at the output terminal.

Abstract: A digital signal system (50) determines an approximate antilog x from a value of ƒ(x), where x has a base b.

Abstract: A method for making a transistor within a semiconductor wafer. The method may include etching a recess at source/drain extension locations 90 and depositing SiGe within the recess to form SiGe source/drain extensions 90. Dopants are implanted into the SiGe source/drain extensions 90 and the semiconductor wafer 10 is annealed. Also, a transistor source/drain region 80, 90 having a SiGe source/drain extension 90 that contains evenly distributed dopants, is highly doped, and has highly abrupt edges.

Abstract: A method comprising loading a plurality of data bytes from a data cache in response to a load instruction, determining the most significant bit of at least one of the data bytes using a first logic, arranging at least some of the data bytes onto a data bus using a second logic substantially coupled in parallel with the first logic, and performing a sign extension on the data bus using the second logic.

Abstract: The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer (110) beneath the gate dielectric (50) and source and drain regions (80) of a MOS transistor. The carbon containing layer (110) will prevent the diffusion of dopants into the region (40) directly beneath the gate dielectric layer (50).

Abstract: The present invention provides a method for manufacturing a metal-insulator-metal (MIM) capacitor, a method for manufacturing an integrated circuit having a metal-insulator-metal (MIM) capacitor, and an integrated circuit having a metal-insulator-metal (MIM) capacitor. The method for manufacturing the metal-insulator-metal (MIM) capacitor, among other steps and without limitation, includes providing a material layer (185) over a substrate (110), and forming a refractory metal layer (210) having a thickness (t1) over the substrate (110), at least a portion of the refractory metal layer (210) extending over the material layer (185). The method further includes reducing the thickness (t2) of the portion of the refractory metal layer (210) extending over the material layer (185), thereby forming a thinned refractory metal layer (310), and reacting the thinned refractory metal layer (310) with at least a portion of the material layer (185) to form an electrode (440) for use in a capacitor.

Abstract: A wireless device 148 that performs link adaptation is disclosed. The wireless device 148 comprises at least two antennas 101a, 120a and 101b, 120b, and a network interface logic operable to select transmission parameters based on a packet error rate 154 and on at least one signal to noise ratio 152 of a radio communication channel.

Abstract: The present invention provides, in one aspect, a method of fabricating a capacitor 615, comprising forming a first electrode 610, placing a dielectric 515 over the first electrode, and locating a second electrode 510 over the dielectric wherein at least one of the first or second electrodes 610, 510 is doped amorphous silicon.

Abstract: The present invention provides a packet prioritizer for use with a wireless local area network (WLAN) access point. In one embodiment, the packet prioritizer includes a priority tagger configured to provide a packet priority for a WLAN packet. Additionally, the packet prioritizer also includes a priority scheduler coupled to the priority tagger and configured to provide a strict priority scheduling of the WLAN packet through the WLAN access point based on the packet priority.

Abstract: When a sample stream is decimated, frequency components from outside of a desired frequency band are aliased into the desired band, causing interference and loss of information. Different decimating ratios result in different frequencies aliasing into the desired frequency band. A current-mode sampling mixer 800 with capacitor banks 811 and 812 that are controlled by a digital control unit 820 with a capability to integrate and decimate an RF current at different decimating ratios is able to measure the frequency spectrum with different decimating ratios. The measured frequency spectrum is then analyzed to detect the presence of interferers aliased into the desired frequency band. The interferers can then be eliminated or avoided.

Abstract: A system (10) and method (30) for precisely depositing a solder compound onto a substrate (18). The system (10) generally includes a receiving member (20) having a rotatable portion (21) adapted to receive a planar substrate (18), a horizontal member (12) for depositing solder balls (11) on the substrate (18), and a contact member (14), located between the receiving member (20) and horizontal member (12). The contact member comprises an aligner plate (14) having a pair of stoppers (15) protruding therefrom. Advantageously, pivotable portion (21) of the system (10) establishes the planarity of the substrate (18), with respect to the horizontal mount (12) allowing for the solder balls (11) to be mounted thereon, preventing the substrate (18) from being slightly misaligned, warped, and/or tilted.

Abstract: An apparatus for controlling output signals at an output locus of a power converting device has a rectifier coupled to receive an input signal and present a rectified input signal for switching connection with one of a first and a second network. The first network includes the rectifier. The second network includes part of the first network and the output locus. The networks establish a return current to the rectifier. The apparatus includes: (a) a current indicating unit coupled with the output locus for combining an extant output signal with a time-integrated signal to present a calculated current signal; and (b) a comparing unit coupled with the first network and the current indicating unit for receiving the return current. The comparing unit drives the switching connection when the calculated current signal and the return current have a predetermined relationship.