Abstract: A computer method of analyzing an integrated circuit (“IC”) masked design data, comprising grouping into a cluster areas of layers preceding a target metal layer that are suitable for milling, deleting portions of the target metal layer that do not meet minimum tool spacing requirements to produce a modified metal layer, deleting portions of the modified metal layer that do not meet minimum design rule width requirements to produce a final metal layer, and comparing the final metal layer and the cluster to identify common areas.

Abstract: The objective of this invention is to reduce the current flowing through the inductance element in a step-up/step-down DC—DC converter and to control the ripple in the output voltage. In the DC—DC converter, four states, that is, the first state [1] of (M1, M2)=(off, on) and (M3, M4)=(on, off), the second state [2] of (M1, M2)=(on, off) and (M3, M4)=(off, on), the third state [3] of (M1, M2)=(on, off) and (M3, M4)=(on, off), and the fourth state [4] of (M1, M2)=(off, on) and (M3, M4)=(off, on) are repeated in a prescribed order, preferably in the order . . . [1]?[4]?[2]?[3]?[1] . . . or . . . [1]?[3]?[2]?[4]?[1] . . . .

Abstract: A system and method for manufacturing semiconductor devices with dielectric layers having a dielectric constant greater than silicon dioxide includes depositing a dielectric layer on a substrate and subjecting the dielectric layer to a plasma to reduce top surface roughness in the dielectric layer.

Abstract: The invention generally provides a method of intelligent frequency hopping such as in Bluetooth and Home RF networks. The method (400) includes the acts of generating windows (410), sampling an original frequency (430), determining if the original frequency is of a desired frequency type (440), using the original frequency when the original frequency is the desired frequency type (460), and mapping the frequency to the desired frequency type when the original frequency is not the desired frequency type (450). Accordingly, the method increases the reliability and throughput of wireless networks.

Abstract: A method (10) of forming a MIM (metal insulator metal) capacitor is disclosed whereby adverse affects associated with copper diffusion are mitigated even as the capacitor is scaled down. A layer of bottom electrode/copper diffusion barrier material (136) is formed (16) within an aperture (128) wherein the capacitor (100) is to be defined. The bottom electrode layer (136) is formed via a directional process so that a horizontal aspect (138) of the layer (136) is formed over a metal (110) at a bottom of the aperture (128) to a thickness (142) that is greater than a thickness (144) of a sidewall aspect (148) of the layer (136) formed upon sidewalls (132) of the aperture (128). Accordingly, the thinner sidewall aspects (148) are removed during an etching act (18) while some of the thicker horizontal aspect (138) remains. A layer of capacitor dielectric material (150) is then conformally formed (20) into the aperture 128 and over the horizontal aspect (138).

Abstract: An improved SLM that is capable of detecting when light incident on the SLM exceeds a predetermined threshold. A diode is fabricated around, or within the pixel array. Light incident on the array (and the diode) results in a current increase through the diode, which may detected and used to initiate a disable signal to control circuitry of the SLM.

Abstract: A circuit topology for gain boosted high-swing folded cascode has been improved to maximize the available dynamic range in applications having low supply voltage requirements. The circuit includes an improved gain boost amplifier that maximizes the available dynamic range for applications having low supply voltage requirements. The improved gain boosting amplifier includes a differential pair of input transistors connected to a current mirror, wherein a pair of current sources supply current to each lead of the current mirror. One lead of the current mirror is level-shifted by a transistor coupled to another current source, wherein the coupling of the transistor and the current source form the output of the amplifier. Effectively, the amplifier consists of a level shifter and a series common-drain, common-gate amplifier. A reduction in transconductance gm from the series combination is compensated by a current mirror ratio (K:1) between the level shift and the common-drain, common-gate amplifier.

Abstract: The present invention provides a virtual machine for use with a general purpose processor (GPP). In one embodiment, the virtual machine includes a register set of the GPP dedicated to retain an execution context corresponding to an interrupt-driven task. The virtual machine also includes an interrupt generator coupled to the register set and configured to provide at least one interrupt event associated with the interrupt-driven task. The virtual machine further includes a virtual processor coupled to the interrupt generator and configured to execute a processing state corresponding to each interrupt event.

Abstract: A phase-locked loop (PLL) architecture (100) is provided that includes a voltage-controlled oscillator (VCO) (116). The PLL architecture (100) also includes a digital calibration loop (132) coupled to the VCO (116). The digital calibration loop (132) implements a digital filter (126) to provide a digital control to the VCO (116) for centering a VCO frequency output. The PLL architecture (100) also includes an analog calibration loop (130) coupled to the VCO (116). The analog calibration loop (130) provides an analog control to the VCO (116) for adjusting the centered VCO frequency output.

Abstract: Interference cancellation/suppression by a wide band radio (100) includes the steps of searching for all narrow band interferer signals such as Bluetooth signals (502). Communicating with the detected Bluetooth piconets (504). Estimating when the Bluetooth signals will occur (506) using the information received during step (504) . And using a suppression technique in association with the estimations as to when/where the interfering signals will occur in order to counter the interfering signal(s). In an alternate embodiment, both the narrow band (304) and wide band (302) signals are stored (306). Then the one or more narrow band Bluetooth signal(s) (304) and decoded (308) and subtracted (308) from the wide band packet prior to it being decoded (312).

Abstract: Disclosed are methods and circuits for impedance-controlled write drivers using matched impedance control circuits coupled in parallel with a magnetic write head.

Abstract: The present invention provides, in one embodiment, a method of manufacturing semiconductor devices. The method comprises transferring one or more substrate into a deposition chamber and depositing material layers on the substrate. The chamber has an interior surface. The method further includes, between the transfers, cleaning the deposition chamber using an in situ ramped cleaning process when material layer deposits in the deposition chamber reaches a predefined thickness. The in situ ramped cleaning process comprises forming a reactive plasma cleaning zone by dissociating a gaseous fluorocompound introduced into a deposition chamber in a presence of a plasma. The cleaning process further includes ramping a flow rate of the gaseous fluorocompound in a presence of the plasma to move the reactive plasma cleaning zone throughout the deposition chamber, thereby preventing a build-up of localized metal compound deposits on the interior surface.

Abstract: A method is provided for generating an image having a plurality of bands. A page description representative of elements of the image is received from an external source. A display list buffer is then built that has a plurality of display list elements (DLE) derived from the page description, each display list element being representative of a corresponding graphic item. A banded display list is then built that is representative of the plurality of bands of the image. For each band of the plurality of bands, a set of templates is stored in the banded dismay list in which each template points to a DLE in the display list buffer for each corresponding graphic item that is spawned within the band. Each band is then rendered by using the set of templates stored for that band to access a corresponding set of DLEs from the display list buffer. In one embodiment, a printer includes a microprocessor with on-chip memory.

Abstract: An aspect of the present invention reduces the effect of any noise present along with an input signal when sampling the input signal by charging each of several parallel connected capacitors for different time durations with at least some non-overlap. In an embodiment, such an approach is used in a switched capacitor amplifier circuit of an ADC. The capacitors in that embodiment start charging at the same time instance, but stop charging at different time instances due to the design of associated switches and control signals.

Abstract: An integrated circuit for use with an external Hall sensor that permits to at least substantially cancel out the temperature drifts of the Hall sensor, as caused by the temperature drift of the current supplied to the Hall sensor, and the gain of the Sigma-Delta modulator. Specifically, the circuit provides an integrated circuit for use with an external Hall sensor, that has an analog input for application of a Hall voltage from the Hall sensor, a digital data output and a current output for connection to a current input of the Hall sensor. The integrated circuit comprises a Sigma-Delta modulator with an input connected to the analog input and an output connected to the digital data output. An internal reference voltage source is also included in the integrated circuit, and an internal current source is connected to the current output for the Hall sensor.

Abstract: A CMOS integrated circuit (15A-B-C) includes both relatively low-power (124, 126) and high-power (132, 134) CMOS transistors on the same chip. A 20V, relatively high-power PMOS device (134) includes a heavily doped N-well drain region (70). A 20V, relatively high-power NMOS device (132) includes heavily doped P-type buried layers (76, 78) underneath the source (94) and drain regions (96) and spanning the gap between the P-well gate (90F) and adjacent P-well isolation regions (46, 50).

Abstract: The present invention pertains to a multi-layer sidewall process (100) that facilitates forming a transistor in a manner that allows adherence to certain design rules while concurrently mitigating adverse effects associated with forming areas of transistors close to one another. First sidewall spacers having first widths are formed (124) alongside a gate structure of a transistor to facilitate implanting source/drain dopants far enough away from the gate structure so that dopant atoms are unlikely to migrate into a channel area under the gate structure. Additionally, the process provides uniform layers for dopant atoms to pass through to mitigate variations in device characteristics across a wafer. The manner of forming the sidewall spacers also allows a salicide blocking process to be simplified. The first sidewall spacers are subsequently reduced (132) to establish second sidewall spacers having second widths which are smaller than the first widths.

Abstract: A method and apparatus for providing multiple queues that share a single memory buffer. A memory buffer is divided into a plurality of fixed length memory segments. Queues are created by chaining one or more memory segments together. Memory segments are allocated on a dynamic basis when needed by a queue. Multiple queues are created wherein each queue consists of a set of one or more memory segments. A list is used to track the memory segments making up a queue. The pointers to the memory segments are stored in a pointer table or a linked list termed a next segment pointer table. Multiple queues are handled by creating multiple linked lists, one for each queue. Each memory segment has associated with it a corresponding next segment pointer. A segment pointer is assigned to each memory segment and is adapted to contain the address of the next segment in the queue.

Abstract: A voltage-to-current conversion circuit includes an error amplifier (12A) which amplifies a voltage difference between the drains of the first (6) and second (7) transistors of a first current mirror, wherein drain current of the first transistor is proportional to an input voltage (Vin). The output of the error amplifier is connected to the gates of the first and second transistors. A compensation capacitor is coupled between the gate and drain of the first transistor. The drain current of the second transistor flows through a cascode transistor (16) to an input of a second current mirror, an output transistor (31) of which provides a current (Ibias) which is proportional to the input voltage (Vin) as a bias current for the error amplifier, to provide stable operation.

Abstract: In support of data processing emulation, a data processing condition indicated by a predetermined number of digital data processing signals can be detected by applying the digital data processing signals to a lookup table (LUT) that is programmable according to how the digital data processing signals (23) indicate the data processing condition. The lookup table is responsive to said digital data processing signals for determining whether said data processing condition exists.