Abstract: A distributed processing system (10) includes a plurality of processing modules, such as MPUs (12), DSPs (14), and coprocessors/DMA channels (16). Power management software (38) in conjunction with profiles (36) for the various processing modules and the tasks to executed are used to build scenarios which meet predetermined power objectives, such as providing maximum operation within package thermal constraints or using minimum energy. Actual activities associated with the tasks are monitored during operation to ensure compatibility with the objectives. The allocation of tasks may be changed dynamically to accommodate changes in environmental conditions and changes in the task list.

Abstract: A variety of bidirectional data transmission systems that facilitate communications between a plurality of remote units (15) and a central unit (10) using a frame based discrete multi-carrier transmission scheme are disclosed. In each of the systems, frames transmitted from the plurality of remote units (15) are synchronized at the central unit (10). A variety of novel modem arrangements and methods for coordinating communications between a plurality of remote units (15) and a central unit (10) to facilitate multi-point-to-point transmission are disclosed. The invention has application in a wide variety of data transmission schemes including Asymmetric Digital Subscriber Line systems that includes the transmission of signals over twisted pair, fiber and/or hybrid telephone lines, cable systems that includes the transmission of signals over a coaxial cable, and digital cellular television systems that include the transmission of radio signals.

Abstract: An inductor integrated in a semiconductor device comprises a first and second lower electrical trace, an upper electrical trace, aligned at a first end with a first end of the first lower electrical trace and at a second end with a second end of the second lower electrical trace, a first via intercoupling the first end of the upper electrical trace with the first end of the first lower electrical trace, and a second via intercoupling the second end of the upper electrical trace with the second end of the second lower electrical trace.

Abstract: System and method for adjusting an operational parameter of a component that drifts with temperature changes. The system includes a torsional hinged device that oscillates at a resonant frequency, and the resonant frequency of the device drifts or varies with temperature. Differences of a selected parameter between a drive signal and the actual selected parameter are monitored to determine changes in the resonant frequency. An output signal representative of change in the resonant frequency is used to adjust another component that also has a parameter that varies with temperature changes. The adjustment compensates for the temperature drift.

Abstract: A differential to single-ended signal transfer circuit that allows increased gain and improved AC performance while reducing power supply voltage requirements. The transfer circuit includes a first operational transconductance amplifier (OTA), a second operational amplifier (OPA), first and second controlled current sources, a third current source, and first and second bipolar junction transistors. The inverting and non-inverting inputs of the transfer circuit are provided at the inverting input and the non-inverting input, respectively, of the OTA, which is coupled to the first and second controlled current sources to form a current mirror with tracking feedback. The output voltage of the transfer circuit is provided at the emitter of the first transistor, the base of which is connected to the non-inverting input INp. The first transistor is coupled to the third current source in an emitter follower configuration to provide both current gain and impedance matching.

Abstract: Methods and systems for communication systems are disclosed. Chirp signals generated according to a chirp rate and carrier frequency are used for communication. The chirp rate can be determined by solving integrals or by simulation of transmission parameters. A chirp signal is transmitted from a base station and delayed versions of the chirp signals are created. The delayed versions are generated by the chirp signal reflecting off of reflectors. A receiving station receives an incoming signal. The incoming signal includes the LOS signal plus delayed versions, noise and/or interference. Unwanted signals, either LOS or delayed versions, noise and/or interference are removed from the incoming signal to obtain the desired chirp signal. Using the chirp rate, the chirp signal is converted to a corresponding digital signal.

Abstract: An apparatus for presenting a substantially linear capacitive output at at least one output locus in response to a voltage input at an input locus, the voltage input varying over a voltage range, includes a plurality of switching units coupled with the input locus. Each respective switching unit of the plurality of switching units is coupled with one output locus of the at least one output locus. Each respective switching unit presents a contributing capacitive output at the one output locus. The contributing capacitive output exhibits a generally linear response to the voltage input over a segment of the voltage range. All the respective switching units cooperate to establish the substantially linear capacitive output over substantially all of the voltage range.

Abstract: A dielectric layer (50) is formed over a semiconductor (10) that contains a first region (20) and a second region (30). A polysilicon layer is formed over the dielectric layer (50) and over the first region (20) and the second region (30). The polysilicon layer can comprise 0 to 50 atomic percent of germanium. A metal layer is formed over the polysilicon layer and one of the regions and reacted with the underlying polysilicon layer to form a metal silicide or a metal germano silicide. The polysilicon and metal silicide or germano silicide regions are etched to form transistor gate regions (60) and (90) respectively. If desired a cladding layer (100) can be formed above the metal gate structures.

Abstract: A method for testing a partially fabricated wafer is provided that comprises the following steps: providing a device under test (DUT) and three reference oscillators overlying a substrate of the wafer; measuring the frequencies of the reference oscillators as influenced by transistor characteristics, intra structure parasitics, resistive, capacitive and inductive parasitics; and isolating the inductive parasitics by the appropriate comparisons between the reference oscillators.

Abstract: A subsampling receiver (50, 50?, 50?) for converting an RF signal to baseband is disclosed. The subsampling receiver (50, 50?, 50?) may be implemented into a wireless communications device (40), such as a wireless telephone handset. In one disclosed embodiment, the receiver (50) includes a sample and hold circuit (80) that samples a bandpass filtered input modulated signal at the subsampling frequency (fs) that is well below the RF carrier frequency but twice the bandwidth (BW) of the payload; the sampled signal is digitized, and applied to two digital mixers (85I, 85Q) to produce in-phase and quadrature components (I,Q) of the payload. In another embodiment, the receiver (50?) includes two sample and hold circuits (96I, 96Q) to sample the filtered signal at different phases of the sampling frequency, to produce the in-phase and quadrature digital components.

Abstract: Cell search synchronization in spread spectrum communications systems using primary and second synchronization codes with symbol partitioning for shorter coherent combinations (despreading) which are combined non-coherently, and Fourier transform analysis automatically adjusts for phase rotation of the despread sub-symbols.

Abstract: The present invention achieves technical advantages as an improved Parallel Damping scheme suitable for very-low-supply preamp operation. The improved Parallel Damping Scheme accurately generates a programmable Iw flowing through the write head while compensating for a leakage current path through a Parallel Damping resistor.

Abstract: An operational amplifier having temperature-compensated offset correction. The amplifier includes an operational amplifier circuit, that has a first input field effect transistor (FET) having a gate connected to receive a first input signal, and a second input FET having a gate connected to receive a second input signal, the first and the second input FETs being connected together to receive a first bias current, and also being connected to respective sides of a first current mirror. A correction amplifier circuit is also provided, that has a first correction FET having a gate, and a second correction FET having a gate, the first and the second correction FETs being connected together to receive a second bias current, and also being connected to respective sides of a second current mirror.

Abstract: A real-time operating system runs on a processor and dynamically manages the power state of individual circuits or resources with the processor. Thus, if a particular circuit is not needed, power to that circuit can be disabled. If a circuit is shut down, any configuration information or other type of data can be saved before powering off the circuit. Power can be re-enabled to the circuit on a responsive or predictive basis and the configuration information and/or data (collectively referred to as “state” information) can be reloaded into the circuit.

Abstract: The present invention provides source/drain electrode 100 for a transistor 105. The source/drain electrode 100 comprises a plurality of polysilicon grains 100 located over a source/drain region 115. A metal salicide layer 120 conformally coats the plurality of polysilicon grains. The present invention also includes a method of fabricating the above described source/drain electrode 200, and integrated circuit 800 have includes a semiconductor device 805 having the described source/drain electrodes 810.

Abstract: An appliance includes a memory having at least a hidden partition of memory. The hidden partition of memory operates to store at least a portion of a program capable of contributing to one or more functions of the appliance. The appliance also includes a controller operable to process at least a portion of the program stored on the hidden portion of memory. The appliance further includes an external interface operable to provide access to at least an open portion of the memory. In one particular embodiment, the hidden portion of memory is inaccessible through the external interface. After modifying the at least a portion of the program, a decrypted update file is deleted from the open portion of memory and the external interface may be reestablished.

Abstract: A digital demodulator employing a digital differential detection mechanism based on extracting phase differences directly from the I and Q signals after downconversion to zero-IF and image rejection are performed. The phase of the input I and Q signals is determined using the principle that the phase is equivalent to arctan ( Q I ) . A lookup table stores the values of the arctan function preferably in a reduced size format. The size of the lookup table can be reduced significantly by storing arctan values for the first quadrant only (i.e. 0 to 90°) and taking advantage of the fact that the phase values for the other three quadrants can be derived from those of the first with some correction applied depending on the signs of the I and Q input samples. Phase extraction logic is provided that is operative to map the phase into the entire 0 to 360° range of phase values (i.e. ?? to +? radians) based on the signs of the I and Q signals.

Abstract: The present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit. The method for manufacturing the semiconductor device, among other steps, includes forming a gate structure (130) over a substrate (110), the gate structure (130) having L-shaped sidewall spacers (430) on opposing sidewalls thereof and placing source/drain implants (310 or 510) into the substrate (110) proximate the gate structure (130). The method for manufacturing the semiconductor device further includes removing at least a portion of a horizontal segment of the L-shaped sidewall spacers (430).

Abstract: Timely testing of die on wafer reduces the cost to manufacture ICs. This disclosure describes a die test structure and process to reduce test time by adding test pads on the top surface of the die. The added test pads allow a tester to probe and test more circuits within the die simultaneously. Also, the added test pads contribute to a reduction in the amount of test wiring overhead traditionally required to access and test circuits within a die, thus reducing die size.

Abstract: Systems and methods for providing a battery module 110 with secure identity information and authentication of the identity of the battery 110 by a host 120. In one embodiment, the system for providing a battery module with secure identity information includes: (1) a tamper resistant processing environment 200 located within the battery module 110 and (2) a key generator configured to generate a key based on an identity of the battery module 110 and cause the key to be stored within the tamper resistant processing environment 200.