Abstract: According to one embodiment of the present invention, a method of forming a semiconductor device includes forming a gate stack on an outer surface of a semiconductor body. First and second sidewall bodies are formed on opposing sides of the gate stack. A first recess is formed in an outer surface of the gate stack, and a first dopant is implanted into the gate stack after the first recess is formed. The first dopant diffuses inwardly from the outer surface of the gate stack that defines the first recess. The first dopant diffuses toward an interface between the gate stack and the semiconductor body. The first recess increases the concentration of the first dopant at the interface.

Abstract: The present invention provides a system for reducing row periphery power consumption in a semiconductor memory device, particularly during sleep mode operation. A memory device (100) according to the present invention has a row (106) of memory cells and driver circuitry (102) preceding the row of memory cells. The present invention provides an intervention circuit (114) instantiated within the driver circuitry proximal to the row of memory cells. The intervention circuit is operated to hold the row of memory cells at a desired state, while the driver circuitry (108, 110) preceding the intervention circuit is powered down.

Abstract: A capacitor (100) is disclosed that is formed as part of an integrated circuit (IC) fabrication process. The capacitor (100) has conductive top and bottom electrodes (140, 144) and a nonconductive capacitor dielectric (142). In one example, the dielectric (142) includes first and second thin dielectric layers (112, 114) that sandwich a layer of antireflective material (118). The thin layers (112, 114) provide the dielectric behavior necessary for the capacitor while the antireflective layer (118) promotes reduced feature sizes by mitigating reflected standing waves, among other things.

Abstract: The present invention provides a system for producing a triple-gate transistor segment (300), utilizing a standard semiconductor substrate (302). The substrate has a plurality of isolation regions (304) formed along its upper surface in a distally separate relationship, defining a channel region (306). A form structure (308) is disposed atop the isolation regions, and defines a channel body area (310) over the channel region. A channel body structure (316) is disposed within the channel body area, and is engineered to provide a blunted corner or edge (318) along a perimeter of its upper exposed surface. The form structure is then removed, and subsequent processing is performed.

Abstract: A method of fabricating an integrated circuit, having copper metallization formed by a dual damascene process, is disclosed. A layered insulator structure is formed over a first conductor (22), within which a second conductor (40) is formed to contact the first conductor. The layered insulator structure includes a via etch stop layer (24), an interlevel dielectric layer (26), a trench etch stop layer (28), an intermetal dielectric layer (30), and a hardmask layer (32). The interlevel dielectric layer (26) and the intermetal dielectric layer (30) are preferably of the same material. A via is partially etched through the intermetal dielectric layer (30), and through an optional trench etch stop layer (28). A trench location is then defined by photoresist (38), and this trench location is transferred to the hardmask layer (32).

Abstract: Methods and apparatus for use in generating data sequences for direct sequence spread spectrum (DSSS) communications are described. One exemplary method includes the steps of serially generating a pseudo random noise (PN) sequence by, for each count value i of a plurality of count values, retrieving from memory a bit of the PN sequence corresponding to the (i)th position in the PN sequence. The exemplary method includes the further steps of serially generating a Gold code sequence by, for each count value i of the plurality of count values, retrieving from memory a bit of the PN sequence corresponding to the (i+n)th position in the PN sequence, retrieving from memory a bit of the PN sequence corresponding to the (q*i)th position in the PN sequence, and adding the bit corresponding to the (i+n)th position with the bit corresponding to the (q*i)th position.

Abstract: A method and circuit for eliminating input voltage offset in an amplifier circuit are provided. An exemplary offset correction circuit is configured with DC restoration to eliminate the DC input voltage offset by suitably providing a correction voltage to correct an input voltage offset during operation of the amplifier circuit, without realizing recovery time problems associated with AC coupling. An exemplary offset correction circuit is configured with DC restoration and comprises a timing circuit, a sample and hold circuit, and a feedback circuit to provide a correction voltage signal to correct input voltage offset. The timing circuit is configured to determine a “dead time” and “live time” for operation of the amplifier circuit. During the “dead time” period the sample and hold circuit will sample a differential signal across the DC coupling and provide a feedback signal through feedback circuit to correct input offset voltage.

Abstract: A processor comprising an instruction cache module adapted to store a plurality of instructions, the plurality of instructions comprising a group of instructions predicated on a conditional statement. The processor also comprises a branch prediction module coupled to the instruction cache module and adapted to predict an outcome of the conditional statement. Based on the prediction, the branch prediction module modifies an instruction preceding the group of instructions such that at least one instruction in the group of instructions is not executed.

Abstract: A system comprising a pipeline in which a first plurality of instructions are processed, and a branch prediction module coupled to the pipeline, where the branch prediction module is adapted to predict the outcomes of at least some branch instructions in the first plurality of instructions and in a second plurality of instructions that have not yet been fetched into the pipeline.

Abstract: The present invention provides a semiconductor device, a method of manufacture therefore and a method for manufacturing an integrated circuit including the same. The semiconductor device, among other elements, may include a substrate (110), as well as a nickel silicide region (170) located over the substrate (110), the nickel silicide region (170) having an amount of indium located therein.

Abstract: A system (12) for determining discrete transforms as between time and frequency domains. The system comprises a grid (60) comprising adders and multipliers. The grid is operable to perform in parallel an integer number P operations of a first transform function selected from one of either an IFFT or an FFT. The system also comprises the integer number of P serially-operating pipelines (641-648). Each of the pipelines is coupled to the grid and is operable to perform serially over a number of cycles an integer number S operations of the first transform. In the system, S and P are both greater than one and, in combination, the grid and the serially-operating pipelines perform the first transform type as an S×P-point transform. In a first instance at least a portion of the grid is operable to perform IFFT operations. In a second instance at least a portion of the grid is operable to perform FFT operations.

Abstract: An program counter address comparator includes two comparators comparing an input program counter address with respective reference addresses. The comparators produce a match indication on selectable criteria, such as greater than, less than, equal to, not equal to, less than or equal to, and greater than or equal to, and can be selectively chained. Input multiplexers permit selection of either the program counter address bus or a secondary address bus. The reference addresses and control functions are enabled via central processing unit accessible memory mapped registers.

Abstract: A bandgap reference circuit as may be used in ultra-low current applications is provided. An exemplary bandgap circuit can be configured to generate a positive temperature coefficient without the need for a resistor to offset a negative temperature coefficient. In accordance with an exemplary embodiment of the present invention, a bandgap circuit comprises a negative temperature coefficient generated from a junction device and a positive temperature coefficient generated from an FET-based device. An exemplary junction device can comprise a bipolar, junction diode or any other device for generating a negative temperature coefficient, while an exemplary FET-based device comprises a gate-drain connected device configured to provide a gate-source voltage having a positive temperature coefficient coupled in series with the bipolar device.

Abstract: A driver apparatus comprising a signal switching circuit coupled for receiving an actuation signal and generating a first and a second control signal in response to the actuation signal; a first control circuit and a second control circuit coupled with the signal switching circuit; the first and second control circuits generating first and second drive control signals in response to the first and second control signals; first and second current generating circuits coupled with the first and second control circuits and coupled with a lower voltage rail; the first and second current generating circuits presenting first and second drive signals at first and second output loci in response to the first and second drive control signals.

Abstract: Systems, methods and circuits for sense circuit calibration. In one particular case, a system is provided that includes a sense circuit, a calibration circuit, and a sample and hold circuit. The sense circuit provides a sense current that is derived from either a reference current or a load current depending upon the operational state. The calibration circuit includes a calibration amplifier electrically coupled to the reference current and to the sense current. The calibration amplifier outputs a calibration signal representing a difference between the reference current and the sense current. The sample and hold circuit is operable to store a value representative of the calibration signal, and useful in forming a calibration offset current applied to the sense current.

Abstract: An evaluator (210) having an input (207) for receiving a signal indicative of a channel current sensed via a sensor in a mutlichannel current sharing system, and circuitry (313, 319) coupled to the input (207) and responsive to the signal for indicating an unreliable sensing for the sensor when a low current condition occurs for a time period exceeding the switching time period of the channel current. Further, the apparatus can include an additional input (207) and circuitry (313, 319) for evaluating an additional sensor sensing an additional channel current. The low current condition is characterized by thresholds corresponding to the peak level and a valley level of the channel current over a switching time period.

Abstract: An apparatus for controlling operation of a processor device during startup of the processor device includes: (a) a signal treating circuit receiving a voltage supply signal at a voltage supply locus; the signal treating circuit using the voltage supply signal for generating a first treated signal and a second treated signal; and (b) an output circuit coupled with the signal treating circuit; the output circuit receiving the first treated signal and the second treated signal and generating a control signal at an output locus based upon a relationship between the first treated signal and the second treated signal; the output locus being coupled with the processor device; the control signal effecting the controlling.

Abstract: To make use of its full input voltage operating range, an analog-to-digital converter is configured with a switched-capacitor circuit to produce a digital output signal from an analog input signal that lies within a range of input signal voltage. The analog-to-digital converter is configured with an amplifier with a digitally programmable gain and a voltage generator with a digitally controlled output voltage. The voltage generator is coupled through a buffer to the amplifier input and generates an output voltage inversely proportional to the amplifier gain. The amplifier gain and the voltage generator output voltage are controllable with the same digital control signal. The combination of the amplifier and the voltage generator can be configured to produce a voltage for the analog-to-digital converter that lies in a prescribed voltage range, avoiding the need to generate substantial current from the voltage generator for a switched-capacitor circuit.

Abstract: A field effect semiconductor device comprising a high permittivity silicate gate dielectric and a method of forming the same are disclosed herein. The device comprises a silicon substrate 20 having a semiconducting channel region 24 formed therein. A metal silicate gate dielectric layer 36 is formed over this substrate, followed by a conductive gate 38. Silicate layer 36 may be, e.g., hafnium silicate, such that the dielectric constant of the gate dielectric is significantly higher than the dielectric constant of silicon dioxide. However, the silicate gate dielectric may also be designed to have the advantages of silicon dioxide, e.g. high breakdown, low interface state density, and high stability. The present invention includes methods for depositing both amorphous and polycrystalline silicate layers, as well as graded composition silicate layers.

Abstract: The present application describes a method of implementing a Viterbi algorithm (VA) for trellis coded modulation (TCM) decoding in communication equipment. According to an embodiment, a branch metric is calculated by adding the absolute value of the real and imaginary parts of a complex vector resulting from the subtraction of a received symbol and a constellation point that is the closest to the symbol in each subset.