Abstract: A system and method are provided to regulate resistance in a discontinuous time hot-wire anemometer. The solution removes supply voltage dependency on the mass airflow output signal. Operating the hot-wire anemometer using discontinuous time regulation offers lower system power, but introduces an inverse supply dependent term in the associated transfer function. This effect is removed by multiplying the output signal via a supply dependent signal.

Abstract: The apparatus for detecting the effects of interconnect resistance and capacitance (RC) in a logic circuit includes a first ring oscillator with the interconnect RC parasitics in a logic circuit and a minimum reference ring oscillator without the interconnect RC parasitic in a logic circuit multiplexed to have common stages to obtain delay with and without the parasitics of the interconnect RC. The frequency difference between the first ring oscillator frequency and the minimum reference ring oscillator frequency is determined to detect the effects of the interconnect RC in the logic circuit.

Abstract: The method of protecting micromechanical structures during a wafer fabrication process. A protective layer 402 is deposited to protect the fragile microstructures during a wafer separation process and a post separation cleanup process. Suitable protective layers 402 typically are plastic and tend to deform or delaminate when the wafer is sawn. The deformation of the protective overcoat during the saw process destroys the structures it is intended to protect. To prevent deformation of the protective layer 402, a brittle layer 404 is deposited on the protective layer 402 to hold the protective layer in place during the saw process. Cured photoresist is a suitable protective layer. The photoresist can be applied to the protective layer using standard processes and cured, typically by baking the photoresist. Once the wafer is separated, the brittle layer may be removed. After the debris created during the saw process is removed, the protective overcoat may be removed.

Abstract: Methods and systems are disclosed that facilitate formation of dielectric layers having a particular composition profile by forming the dielectric layer as a number of sub-layers. The sub-layers are thin enough so that specific relative compositions can be achieved for each layer and, therefore, the sub-layers collectively yield a dielectric layer with a particular profile. The formation of individual sub layers is accomplished by controlling one or more processing parameters for a chemical vapor deposition process that affect relative compositions. Some processing parameters that can be employed include wafer temperature, pressure, and precursor flow rate.

Abstract: A DC—DC converter, which can respond quickly and suitably to changes in input voltage within the scope of normal operating conditions to return to the normal operating state. The DC—DC converter is comprised of switching power supply unit 10, which can turn on/off switching elements that can be turned on/off at high frequency to convert a DC input voltage Vin into a DC output voltage Vout, and a control unit 12, which is used to control the on/off operation of the switching elements of said switching power supply unit 10. In control unit 12, when DC output voltage Vout is out of the range of monitoring value AM, the response characteristic of the feedback loop (especially the response characteristic of error amplifier 14) is switched to a greater responsivity to continue the switching control operation of the control system without stopping it.

Abstract: Blind transport format detection with sliding window trace-back for evaluating decodings to candidate block lengths together with piecewise linear approximation of the reliability figure (logarithm of ratio of maximum survivor path metric minus minimum survivor path metric divided by 0 state path metric minus minimum survivor path metric) with a small lookup table plus simple logic.

Abstract: A switching mode converter, having a switching transistor and an inductor, has a discontinuity detector coupled to the inductor which detects when the converter enters the discontinuous mode. The discontinuity detector determines the portion of the cycle of the switching transistor in which the converter is in the discontinuous mode. A feedback controller is coupled to the output of the converter and to the discontinuity detector which alters a feedback control signal of the converter.

Abstract: A FET switching transistor for the solenoid coil of an ABS braking system can switched ON or OFF in no more than substantially 250 ns. A higher current biasing circuit for fast turn on of the FET switching transistor is disconnected when it is necessary to limit the current flowing therethrough, whether during the inrush current to the solenoid coil or due to a fault in the system. The high speed switching of the FET switching transistor causes ringing of the current through the transistor which causes the current detector circuit to exit the current control mode. A deglitch circuit prevents the current detector from exiting the current control mode, so that a timer can be used to turn off the FET switching transistor before it can be damaged by the heat generated during current limit operation.

Abstract: A Propagation Test instruction, a Decay Test instruction and a Cycle Test instruction provide testing of DC and AC interconnect circuits between circuits including JTAG boundary scan cells. A few additions to the Test Access Port circuitry and the boundary scan cells are required to implement the additional instructions. The instructions are extensions of the conventional JTAG operating structure.

Abstract: A method of fabricating improved vias in a multilayer MEMS device. Via seats are patterned into first layer, such that each via will have a via seat at the bottom of the via opening. The via openings are then patterned into a second layer. A third layer of material is deposited, such that the material at least partly fills the via opening and the via seat. The material forms a support post that is anchored to the first layer by means of the material in the via seat.

Abstract: Embodiments of the present invention include systems and methods for load balancing audio/video streams to maximize the number of video frames that are actually rendered on a target device, thus giving the user of the target device a higher quality playback experience. Some embodiments are directed to transcoding an audio/video stream into a format that allows additional decoding time on a target device for more complex video sections of the stream. Additional decoding time is gained by duplicating lower complexity video frames in the video stream that precede the complex video sections and temporally expanding the audio stream by a small percentage around each of these load-balanced windows in the video stream. Other embodiments are directed to identifying the more complex video sections in real-time as the stream is being decoded on a target device, and temporally expanding the audio stream to allow more decoding time for these complex sections.

Abstract: Managing temperature of a read/write head (120) in a disk drive system in which there is a power variance due to different operation modes. A circuit device (100) determines and delivers additional power needed for compensating for the temperature variance due to different operational power requirements. The power is delivered to a resistive heater (Rheat) associated with the head (120). The compensating power is based on the delivery voltage, delivery current, and resistance of the resistive heater (Rheat). The delivery current is varied to account for changes in the resistance of the resistive heater (Rheat) since it can vary with temperature. By sensing the current with a sensor (13), the resistance is determined via the sensed current and the delivery voltage. The current is adjusted for maintaining the compensating power.

Abstract: In one embodiment, a method for probing a wafer includes providing a plurality of pressure sensors on a surface of a probe card holding tray, positioning a probe card of a testhead relative to a prober supporting a wafer, engaging the probe card with the probe card holding tray, receiving a plurality of pressure signals from respective pressure sensors, and comparing the pressure signals to determine if the probe card is substantially parallel with the prober.

Abstract: A computerized system and method for customizing bond programs in order to compensate first for variabilities in an integrated circuit (IC) “slave” bonder, and second to any irregularities in a “slave” circuit positioned on the slave bonder for attaching connecting bonds onto the IC bond pads. According to the invention, a “master” segmentator groups the bond pads of a “master” circuit on a master bonder into segments and stores the reference data related to these segments in a master file. Next, a slave regenerator, coupled to the master file, regenerates the master reference data so that variable characteristics of the slave bonder are defined and adaptively compensated. Finally, a slave corrector, coupled to the salve regenerator, corrects the bond program for the slave circuit on the adaptively compensated slave bonder. The slave bonder attaches the connecting bonds based on the computed correct bond locations.

Abstract: A CDMA receiver is provided which is operable to receive a CDMA encoded signal and decode the information therein utilizing a selected code. The systems utilizes a plurality of multiply-accumulation blocks (40) which are operable to receive the signal and compare the received signal with a Walsh-Hadamard code. The comparison and the accumulation is made only in the middle of a chip clock with the edges thereof blanked. This information in the middle of the chip clock is accumulated in an accumulator, the MAC (40), for a symbol period. This is then compared with a look up table and then a decision made as to the logic value thereof.

Abstract: A variety of bi-directional data transmission systems that facilitate communications between a plurality of remote units (15) and a central unit (10) using a frame based discrete multi-carrier transmission scheme are disclosed. In each of the systems, frames transmitted from the plurality of remote units (15) are synchronized at the central unit (10). A variety of novel modem arrangements and methods for coordinating communications between a plurality of remote units (15) and a central unit (10) to facilitate multi-point-to-point transmission are disclosed. The invention has application in a wide variety of data transmission schemes including Asymmetric Digital Subscriber Line systems that includes the transmission of signals over twisted pair, fiber and/or hybrid telephone lines, cable systems that includes the transmission of signals over a coaxial cable, and digital cellular television systems that include the transmission of radio signals.

Abstract: A sequential color display system using a white light source to create a full color image projected onto an image plane. A dynamic filter, typically a series of moving dichroic filters, generates a series of primary colored light beams that are swept across the surface of a spatial light modulator. Typically all three primary colors are produced simultaneously by the dynamic filter. The illuminated portion of the dynamic filter is imaged onto the modulator and controller provides appropriate image data for each portion of the modulator in synchronization with the sweep of the primary color bands across the modulator surface. The primary color bands are modulated by the spatial light modulator and the modulated light is focused by lens onto the image plane. The viewer integrates the light arriving at each portion of the image plane over a frame period to provide the perception of a full-color image.

Abstract: A cleaning chemistry for lowering defect levels on the backside of a semiconductor wafer after chemical mechanical planarization (CMP). In a preferred embodiment of the present invention, a cleaning chemistry comprising nitric acid, hydrofluoric acid, and phosphoric acid in solution with deionized water is applied to the wafer surface to be cleaned preferably while subjected to megasonic assist cleaning. The wafer is preferably then subjected to brush scrubbing and a deionized water rinse with megasonic assist cleaning.

Abstract: An amplifier apparatus having a gain programmable in discrete increments includes: (a) an operational amplifier having a first and second input and an output; (b) a feedback circuit between the output and the second input; (c) a reference signal source and supply circuit coupled with the first input; (d) a first resistor network coupled between a first signal locus and the first input conveying a first input signal to the first input and including a first plurality of parallel-connected first resistors; selected first resistors being independently coupled in a first connecting with the first input; (e) a second resistor network coupled between a second signal locus and the second input conveying a second input signal to the second input and including a second plurality of parallel-connected second resistors; selected second resistors being independently coupled in a second connecting with the second input.

Abstract: The objective of the invention is to provide a type of semiconductor memory device equipped with an error correction circuit 200 characterized by the fact that it can perform correction of errors in stored data without increasing the circuit size and power consumption, and without decreasing operating speed. An error correction code EC corresponds to data stored in sub-memory 120 separate from main data stored in main memory 110. In read mode, the main data and error correction code are read from the main memory and sub-memory, respectively. On the basis of these data, the error correction code is generated for correcting errors in the read data. Error correction circuit 300 corrects errors in the main data. By storing the error correction code in a sub-memory different from the main memory and selecting the appropriate layout of the main memory and sub-memory, it is possible to increase the reading speed of the error correction code and to suppress time delays caused by error correction.