Patents Assigned to Texas Instruments
  • Hard disk storage system including a first transistor type and a second transistor type where a first voltage level pulls one of a first pair of transistors and a second voltage level pulls one of a second pair of transistors at substantially the same time
    Patent number: 7068454
    Abstract: A write driver produces balanced voltages across head by using the input write data drive transistors of a slower transistor type (typically PNP) on one half of an H-bridge configuration, while transistors of a faster transistor type (typically NPN) in the other half of the H-bridge configuration are driven indirectly by transistors of the slower type, with a trans-resistance in series with transistors of the faster type. Accordingly, the voltage nodes on either side of the write head are pulled to Vcc and Vee symmetrically. A trans-resistance block (40) uses current sources to pull current from capacitive nodes for faster switching.
    Type: Grant
    Filed: December 30, 2003
    Date of Patent: June 27, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Jeremy Kuehlwein, Scott Sorenson
  • Switched-capacitor circuits with reduced finite-gain effect
    Patent number: 7068203
    Abstract: Operational amplifier circuits (20, 30) including error capacitors (C3, C13) for storing finite gain effect error voltages for correction of output voltages of the circuits (20, 30), are disclosed. The circuits (20, 30) are operated in a sample clock phase to produce an approximation of the output voltage, using negative polarity versions of the input voltages to the circuit. The approximate output voltage is used to produce and store an error voltage, corresponding to the differential voltage at the input of the operational amplifier (15, 25), relative to virtual ground. This error voltage is then subtracted from the input voltage applied in the operate clock phase, to correct for the finite gain effect. A pipelined analog-to-digital converter (50) using the disclosed operational amplifier circuits (20, 30) is also disclosed.
    Type: Grant
    Filed: December 31, 2003
    Date of Patent: June 27, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Franco Maloberti, Martin K. Kinyua
  • System and method to automatically stack and unstack Java local variables
    Patent number: 7069415
    Abstract: A processor preferably comprises a processing core that generates memory addresses to access a memory and on which a plurality of methods operate, a cache coupled to the processing core, and a programmable register containing a pointer to a currently active method's set of local variables. The cache may be used to store one or more sets of local variables, each set being used by a method. Further, the cache may include at least two sets of local variables corresponding to different methods, one method calling the other method and the sets of local variables may be separated by a pointer to the set of local variables corresponding to the calling method.
    Type: Grant
    Filed: July 31, 2003
    Date of Patent: June 27, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Gerard Chauvel, Maija Kuusela, Dominique D'Inverno
  • Operational transconductance amplifier input driver for class D audio amplifiers
    Patent number: 7068103
    Abstract: An audio preamplifier (10) based on an operational transconductance amplifier, in combination with a class D audio output amplifier (12) is disclosed. The input signal is coupled to the preamplifier (10) through a capacitor (14) in series with a resistor (17) that sets the transconductance of the preamplifier. The preamplifier (10) includes a differential operational amplifier (20) that drives output MOS transistors (22a, 22b), which are biased by current sources (24a, 26a; 24b, 26b). Feedback from the drain nodes of the output MOS transistors (22a, 22b) to the inputs of the differential operational amplifier (20), along with the series capacitor (14) and resistor (17) input coupling, ensures minimum offset voltage and current at the output of the preamplifier (10). Common mode feedback control amplifiers (25, 29) ensure proper bias of the components into the saturation region.
    Type: Grant
    Filed: April 30, 2004
    Date of Patent: June 27, 2006
    Assignee: Texas Instruments Incorporated
    Inventor: Ryan E. Lind
  • Reading data from a memory with a memory access controller
    Patent number: 7069485
    Abstract: A serial scan path communication architecture includes a plurality of circuits (30), some of which may include a memory (36). A memory access controller (38) is included in circuits with a memory (36) such that serial data may be written to and written from the memories without having to repetitively cycle through multiple TAP read or write operations operations.
    Type: Grant
    Filed: October 28, 2003
    Date of Patent: June 27, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Lee Doyle Whetsel, Jr., Benjamin H. Ashmore, Jr.
  • Hydrogen free integration of high-k gate dielectrics
    Patent number: 7067434
    Abstract: The present invention pertains to forming a transistor in the absence of hydrogen, or in the presence of a significantly reduced amount of hydrogen. In this manner, a high-k material can be utilized to form a gate dielectric layer in the transistor and facilitate device scaling while mitigating defects that can be introduced into the high-k material by the presence of hydrogen and/or hydrogen containing compounds.
    Type: Grant
    Filed: December 22, 2003
    Date of Patent: June 27, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Luigi Colombo, James J. Chambers, Mark R. Visokay
  • Method for etch-stop layer etching during damascene dielectric etching with low polymerization
    Patent number: 7067435
    Abstract: The present invention provides a method for etching a substrate 100. The method includes conducting a first etch through a dielectric layer 130 located over an etch-stop layer 140, the dielectric layer having a photoresist layer 170 located thereover and the first etch being selective to the etch-stop layer 140. A second etch different from the first etch is conducted on the etch-stop layer 120, the second etch including nitrogen and at least one fluorocarbon gas, such that the ratio of nitrogen to carbon in the etchant is greater than about 5:1.
    Type: Grant
    Filed: September 29, 2004
    Date of Patent: June 27, 2006
    Assignee: Texas Instruments Incorporated
    Inventor: William W. Dostalik
  • High speed pre-driver with voltage reference for thin film head write driver
    Patent number: 7068450
    Abstract: A preamplifier device (26) for a thin film transducer disk drive system having operation speeds up to and greater than 2 Gb/s. The device (26) includes a low power/high speed driver (203) having a cascaded Class AB buffer. In at least one embodiment the device (26) includes separated drive devices in the driver (203) and H-bridge circuit (205) realized in multiple smaller devices biased separately to reduce transistor self-heating effects and a further embodiment includes a reference (201) having a base cancellation scheme and a Class AB current source for improving accuracy and stability is such high speed devices.
    Type: Grant
    Filed: February 25, 2004
    Date of Patent: June 27, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Tuan Van Ngo, Raymond Elijah Barnett
  • Lamp reflector assembly
    Patent number: 7066608
    Abstract: A lamp assembly having a reflector (102) holding a lamp element, or burner (104). The reflector (102) typically is an ellipse, with the burner arc positioned at one foci of the ellipse. A reflector extension (108) is designed to mate to the reflector (102). The reflector extension (108) has a first open end toward the reflector (102). The first open end typically is in contact with the reflector (102) to form a seal around the perimeter preventing glass shards from escaping between the reflector (102) and reflector extension (108). Preferably, the reflector extension (108) contacts the reflector (102) around the perimeter of the reflector (102). The second end of the reflector extension (108) also is open to allow the light from the arc to exit the reflector extension (108). A transparent plate (110) placed across this second open end prevents glass from leaving the reflector extension (108).
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: June 27, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Michael T. Davis, Chris A. Triska, John T. McKinley
  • Design of integrated circuit package using parametric solids modeller
    Patent number: 7068270
    Abstract: A computer is used to model objects by accepting commands from a user. The object is altered in response to the commands. Dimensions are formed between the features, and relations between the dimensions are formed in order to present inconsistence relations which prevent the object from being modeled.
    Type: Grant
    Filed: December 2, 1994
    Date of Patent: June 27, 2006
    Assignee: Texas Instruments Incorporated
    Inventor: Anthony M. Chiu
  • Damage-free resist removal process for ultra-low-k processing
    Patent number: 7067441
    Abstract: A process for removing resist (114) from a CDO dielectric material (110) that uses a non-damaging plasma in a reducing atmosphere under high power and using a structure (150) or other means to limit ions from the plasma from reaching the surface of the CDO material (110).
    Type: Grant
    Filed: November 6, 2003
    Date of Patent: June 27, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Patricia B. Smith, Phillip D. Matz
  • Systems and methods for mismatch cancellation in switched capacitor circuits
    Publication number: 20060132341
    Abstract: Various circuits, systems and methods are disclosed for providing double-sampling sigma-delta modulator circuits. For example, circuits are disclosed that include an amplifier with an integrating capacitor, a switched capacitor conversion element that includes a single capacitor bank, and a control element that provides phase signaling that identifies at least two phases. In operation, charge present on the single capacitor bank is transferred to the integrating capacitor and the single capacitor bank is charged during one phase. During the other phase, charge present on the single capacitor bank is transferred to the integrating capacitor, and the single capacitor bank is discharged.
    Type: Application
    Filed: June 23, 2005
    Publication date: June 22, 2006
    Applicant: Texas Instruments Incorporated
    Inventors: Jinseok Koh, Alexander Reyes
  • System and method of data communication using turbo trellis coded modulation combined with constellation shaping with or without precoding
    Patent number: 7065147
    Abstract: A technique that combines a turbo trellis coded modulation (TTCM) coding scheme with constellation shaping and precoding schemes to implement a binary coded communication system and method that can achieve high performance (high coding gains achieved in combination with shaping gain, and when necessary, also with high performance in ISI-channels via preceding).
    Type: Grant
    Filed: June 22, 2001
    Date of Patent: June 20, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Lior Ophir, Naftali Sommer, Ofir Shalvi
  • Precision jitter-free frequency synthesis
    Patent number: 7065172
    Abstract: An electronic system (10) includes a phase-locked loop (30) and a frequency synthesis circuit (20), for generating a jitter-free output clock (CLK1, CLK2) at a desired frequency. The phase-locked loop (30) includes a voltage-controlled oscillator (37) that produces a number (N) of equally spaced clock phases at a frequency (fVCO) that depends also upon a programmable feedback frequency divider (38) and a prescale divider (32). The frequency synthesis circuit (20) generates the output clock (CLK1, CLK2) at a frequency under the control of a frequency select word (FREQ) that indicates the number of clock phases between successive clock edges. A central processing unit (12), either itself or from a look-up table (13), generates a feedback divide integer (M) and the frequency select word (FREQ) according to a desired frequency (f), by way of a minimization of the frequency error.
    Type: Grant
    Filed: February 26, 2003
    Date of Patent: June 20, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Liming Xiu, Zhihong You
  • Bias system and method
    Patent number: 7064607
    Abstract: A bias device that modifies the bias of a device based on an input signal to the device. The device may have a fixed bias, and the bias device can be connected in parallel with the fixed bias. The device can be an amplifier, such as a linear amplifier or a class AB amplifier. The bias device can be configured to provide maximum bias during the device's crossover time period.
    Type: Grant
    Filed: December 29, 2003
    Date of Patent: June 20, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Kenneth George Maclean, Suribhotla Venkata Rajasekhar, David John Baldwin, Marco Corsi, Tobin Hagan
  • System and method for providing a write strobe signal to a receiving element before both an address and data signal
    Patent number: 7065669
    Abstract: A method and apparatus is provided for that includes an improved special function register (SFR) access scheme by using a clock tree distribution process. In accordance with an exemplary embodiment, a conditional SFR write strobe signal may be used to trigger the SFR registers. A clock tree distribution process may be used to achieve significantly higher system speed. When balancing the clock network of the system, the clock leaf of the flip-flop or other circuit element that generates the SFR write strobe signal may be “advanced” by connecting the circuit element directly to the clock root. In addition, the SFR write strobe signal distribution may be balanced as a separate clock tree with minimum insertion delay.
    Type: Grant
    Filed: May 6, 2002
    Date of Patent: June 20, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Hugo Cheung, Lu Yuan, Terence Chiu
  • Advanced CMOS using super steep retrograde wells
    Patent number: 7064399
    Abstract: The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer (110) beneath the gate dielectric (50) and source and drain regions (80) of a MOS transistor. The carbon containing layer (110) will prevent the diffusion of dopants into the region (40) directly beneath the gate dielectric layer (50).
    Type: Grant
    Filed: September 7, 2001
    Date of Patent: June 20, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Jeffrey A. Babcock, Angelo Pinto, Scott Balster, Alfred Haeusler, Gregory E. Howard
  • Relaxation oscillator based keypad decoder
    Patent number: 7064682
    Abstract: The keypad interface element of this invention uses a relaxation oscillator and a digital keypad processor having a counter/timer to decode specific keys. The RC portion of the relaxation oscillator includes a resistance ladder and a set of momentary on pushbutton switches disposed change resistance dependent upon which key is pressed. This causes the relaxation oscillator to produce an output signal having a corresponding frequency. The counter/timer of the digital keypad processor produces a count corresponding to the oscillator frequency. The digital keypad processor latches and holds a binary number specifically identifying the depressed key. A state machine in the digital keypad processor provides transient-free, noise immune keypad decoding.
    Type: Grant
    Filed: June 5, 2003
    Date of Patent: June 20, 2006
    Assignee: Texas Instruments Incorporated
    Inventor: Stephen J. Fedigan
  • Using quadrant shifting to facilitate binary arithmetic with two's complement operands
    Patent number: 7065699
    Abstract: Operands (90) that are represented in two's complement format are prepared for use in binary arithmetic. For each operand, it is determined (91, 93) whether an original value thereof is within a predetermined proximity of a maximum positive/maximum negative value boundary associated with the two's complement format. If any of the original operand values is within the predetermined proximity, all of the original operand values are adjusted (95) to produce respectively corresponding adjusted operand values (96) for use in a binary arithmetic operation.
    Type: Grant
    Filed: October 26, 2001
    Date of Patent: June 20, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Tod David Wolf, Alan Gatherer
  • Wafer bonded MOS decoupling capacitor
    Patent number: 7064043
    Abstract: A technique for forming a MOS capacitor (100) that can be utilized as a decoupling capacitor is disclosed. The MOS capacitor (100) is formed separately from the particular circuit device (170) that it is to service. As such, the capacitor (100) and its fabrication process can be optimized in terms of efficiency, etc. The capacitor (100) is fabricated with conductive contacts (162) that allow it to be fused to the device (170) via conductive pads (172) of the device (170). As such, the capacitor (100) and device (170) can be packaged together and valuable semiconductor real estate can be conserved as the capacitor (100) is not formed out of the same substrate as the device (170). The capacitor (100) further includes deep contacts (150, 152) whereon bond pads (180, 182) can be formed that allow electrical connection of the capacitor (100) and device (170) to the outside world.
    Type: Grant
    Filed: December 9, 2004
    Date of Patent: June 20, 2006
    Assignee: Texas Instruments Incorporated
    Inventor: Richard P. Rouse