Patents Assigned to Texas Instruments
  • Patent number: 6778005
    Abstract: The present invention improves on the topology of a conventional current source by interposing an RC circuit and additional MOS between the output of a buffer and the output of the current source. The topology of the present invention advantageously provides a clean current output by shunting noise to ground.
    Type: Grant
    Filed: December 27, 2002
    Date of Patent: August 17, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Futoshi Fujiwara, Akihiko Miyanohara
  • Patent number: 6778014
    Abstract: A Complementary CMOS differential amplifier has automatic operating point adjustment (self-biasing) and the properties of a rail-to-rail amplifier. The CMOS differential amplifier uses folded cascodes and is considerably faster in operation than previous CMOS differential amplifiers, since it comprises a circuit element that ensures that, during the operation of the CMOS differential amplifier, all MOS FETs of the cascodes operate in their saturation range (that is not in their resistive range). The CMOS differential amplifier may be used in an input stage, a signal distribution circuit and a clock pulse distribution circuit.
    Type: Grant
    Filed: February 25, 2003
    Date of Patent: August 17, 2004
    Assignee: Texas Instruments Deutschland GmbH
    Inventor: Fred S. Rennig
  • Patent number: 6777300
    Abstract: A polysilicon layer of a gate structure is covered by an implant blocking layer (e.g., silicon nitride). The implant blocking layer blocks introduction of implanted dopants while implanting an initial dose of first conductivity type dopant (e.g., for drain extension regions). The implant blocking layer is then removed and an additional dose of first conductivity type dopant in implanted to form the main source/drain regions. Then, metal is deposited and reacted to form a conductive silicide.
    Type: Grant
    Filed: December 19, 2001
    Date of Patent: August 17, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Jorge Adrian Kittl, Qi-Zhong Hong
  • Publication number: 20040156371
    Abstract: A high speed parser containing a content addressable memory (CAM) providing select values to multiplexers. The CAM is programmed to implement search rules which examine input data for specific semantics according to a protocol, and outputs the specific bit positions at which the corresponding desired data units are present. The outputs are provided to multiplexers to cause the desired data units to be selected on the corresponding output paths of the multiplexors.
    Type: Application
    Filed: February 11, 2003
    Publication date: August 12, 2004
    Applicant: Texas Instruments Incorporated
    Inventors: Pamela Kumar, Cyril John Chemparathy, Mohit Sharma
  • Publication number: 20040155695
    Abstract: A multiplexer containing multiple cells sharing a common output line. The cells select one of multiple input bits. The output line is first charged to a first logical value (e.g., 0), and one of the cells drives the output line to a second logical value (1) if the corresponding input bit does not equal the first logical value. The remaining cells may not affect the output line. Due to such an implementation, the number of transistors may be reduced.
    Type: Application
    Filed: February 11, 2003
    Publication date: August 12, 2004
    Applicant: Texas Instruments Incorporated
    Inventors: Pamela Kumar, Mohit Sharma
  • Publication number: 20040158443
    Abstract: A master scheduler which interfaces with several heterogenous simulators simulating individual modules of an integrated circuit. The master scheduler receives data indicating the modules assigned to each simulator and the interconnections of the modules. The master scheduler forwards output signals generated by one simulator to any other simulators as specified by the interconnection data. As a result, functional verification of an entire integrated circuit can be performed even if only portions can be simulated by corresponding simulators.
    Type: Application
    Filed: February 11, 2003
    Publication date: August 12, 2004
    Applicant: Texas Instruments Incorporated
    Inventor: Raghuraman Rajanarayanan
  • Patent number: 6775778
    Abstract: A secure computing system stores a program, preferably the real time operating system, that is encrypted with a private key. A boot ROM on the same integrated circuit as the data processor and inaccessible from outside includes an initialization program and a public key corresponding to the private key. On initialization the boot ROM decrypts at least a verification portion of the program. This enables verification or non-verification of the security of the program. The boot ROM may store additional public keys for verification of application programs following verification of the real time operating system. Alternatively, these additional public keys may be stored in the nonvolatile memory. On verification of the security of the program, normal operation is enabled. On non-verification, system could be disabled, or that application program could be disabled. The system could notify the system vendor of the security violation using the modem of the secure computing system.
    Type: Grant
    Filed: May 19, 1999
    Date of Patent: August 10, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Frank L. Laczko, Sr., Edward Ferguson
  • Patent number: 6775732
    Abstract: This invention comprises a multiple transaction advanced high performance bus AHB system using two separate fully autonomous AHB buses, each having its own bus arbitration system with decoding to allow for simultaneous activity on the two AHB buses. The two buses are separated by and synchronized with an AHB-to-HTB bus bridge. The first bus, the Memory Bus AHB, contains the CPU and DMA as bus masters and the external memory controller and internal memory as slaves. The second bus, the Data Transfer Bus HTB, contains the high performance peripheral and any local RAM required.
    Type: Grant
    Filed: August 17, 2001
    Date of Patent: August 10, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Steven R. Jahnke, Hiromichi Hamakawa
  • Patent number: 6774455
    Abstract: A method for manufacturing a semiconductor device includes forming a buried layer of a semiconductor substrate. An active region is formed adjacent at least a portion of the buried layer. At least part of the active region is removed to form a shallow trench opening. A dielectric layer is formed proximate the active region at least partially within the shallow trench opening. At least part of the dielectric layer is removed to form a collector contact region. A collector contact may be formed at the collector contact region. The collector contact may be operable to electrically contact the buried layer.
    Type: Grant
    Filed: September 30, 2002
    Date of Patent: August 10, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Jeffrey A. Babcock, Christoph Dirnecker, Angelo Pinto, Scott G. Balster, Michael Schober, Alfred Haeusler
  • Patent number: 6774489
    Abstract: An integrated circuit structure (8) includes a plurality of solid state electronic devices and a plurality of conductive elements (12, 14) that electrically couple the electronic devices. The integrated circuit structure (8) also includes a dielectric layer (16) positioned between two or more of the conductive elements (12, 14). A liner (18) is positioned between at least a portion of the dielectric layer (16) and a conductive element (12, 14). The liner (18) is formed from a compound that includes silicon and either carbon and nitrogen.
    Type: Grant
    Filed: August 23, 2001
    Date of Patent: August 10, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Steven W. Russell, Wei William Lee
  • Patent number: 6775649
    Abstract: A decoder for packetized speech with differential quantization of line spectral frequencies and fixed-codebook gain conceals erased frames with interpolation of future and past frames by reconstruct future frame predicted parameters from presumed interpolations of erased frame parameters.
    Type: Grant
    Filed: August 15, 2000
    Date of Patent: August 10, 2004
    Assignee: Texas Instruments Incorporated
    Inventor: Juan-Carlos DeMartin
  • Patent number: 6775801
    Abstract: This invention presents a unique implementation of the extrinsic block the turbo decoder that solves the problem of generation and use of precision extension and normalization in the alpha and beta metrics blocks. Both alpha metric inputs and beta metric inputs are processed via a circle boundary detector indicating the quadrant of the two's complement input and a precision extend block receiving an input and a corresponding circle boundary input. An extrinsics block includes a two's complement adder of the precision extended alpha and beta metrics inputs. The proposed solution obviates the need for normalization in the alpha and beta metric blocks.
    Type: Grant
    Filed: July 24, 2002
    Date of Patent: August 10, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Tod D. Wolf, Antonio F. Mondragon-Torres
  • Patent number: 6775078
    Abstract: A circuit and method are presented for detecting a fault in a magneto-resistive head (18). The circuit includes a bias circuit (50) to produce a bias voltage across the head (18) and a pair of resistors (68,70) in series with the head (18) connected to the bias circuit (50) to carry a current (IVMR) from the bias circuit (50) in common with the head. A circuit (102,102′) is provided to determine a ratio of a voltage across the head (18) with respect to a voltage across the head (18) and the pair of resistors (68,70), and a circuit (104,106,104′,106′) is provided for indicating a fault if the ratio falls outside a predetermined range.
    Type: Grant
    Filed: September 14, 2001
    Date of Patent: August 10, 2004
    Assignee: Texas Instruments Incorporated
    Inventor: Hong Jiang
  • Patent number: 6774457
    Abstract: A repair fuse element and method of construction are disclosed that eliminate or substantially reduce the disadvantages and problems associated with prior fuse elements. In one embodiment, the fuse element is constructed with a rectangular-shaped contact. The contact is made long enough so that it makes contact at each end with a metal layer, but design rule spacing is still maintained between the connections with the metal layer. The overlapping areas between the rectangular contact and the metal layers are asymmetrical. Alternatively, these overlapping areas are smaller than the design rule overlap requirements. In a second embodiment, a fuse element is constructed with a plurality of rectangular-shaped contacts. As a result, a current value that is significantly lower than conventional fuse current values, can be used to melt such a contact or blow the fuse.
    Type: Grant
    Filed: September 5, 2002
    Date of Patent: August 10, 2004
    Assignee: Texas Instruments Incorporated
    Inventor: Andrew T. Appel
  • Patent number: 6774485
    Abstract: A carrier and package for plural semiconductor devices includes a member with device-conformal apertures therethrough. A first removable cover is attached to one side of the member to close one end of each aperture. After devices are inserted into the apertures with their first ends “up” and their second ends “down,” a second removable cover is attached to the other side of the member to close the other end of each aperture. After inverting the assembly, removal of the first cover presents the devices in the apertures with their second ends “up” and their first ends “down.
    Type: Grant
    Filed: December 29, 2001
    Date of Patent: August 10, 2004
    Assignee: Texas Instruments Incorporated
    Inventor: Lance Cole Wright
  • Patent number: 6775335
    Abstract: A symbol detector provides a delay-less estimate of a transmitted symbol. The symbol detector includes a symbol input for receiving a sequence of input symbols, a plurality of accumulators (ACC) for storing trellis state costs, a plurality of adders (202) for summing the square of distances between an input symbol and a constellation symbol for a trellis branch with the trellis state costs, and a plurality of comparators (203) connected to the adders for determining minimum costs and providing those costs to the accumulators. A memory (201) is connected to an associated comparator for storing the minimum cost determined the associated comparator. A minimization unit (204) outputs an index value of comparators with the lowest value, and a branch table unit (205) outputs a delay-less estimate of a transmitted symbol based on the index of the trellis branch with lowest cost that enters the trellis state with lowest cost and an input symbol.
    Type: Grant
    Filed: April 2, 2003
    Date of Patent: August 10, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Naftali Sommer, Ofir Shalvi
  • Patent number: 6774916
    Abstract: A method and system for displaying fractional bit data in order to increase the bit depth of a PWM display without requiring the use of an excessive number of bit planes. One embodiment of the present invention combines the outputs of two random number generators (702) with the outputs of a row counter (704) and column counter (706) to yield row and column indexes into two 32×32 cell blue noise masks. The row and column indexes select a blue noise mask threshold for a given pixel. The threshold from the first blue noise mask (708) is applied to a comparator (710) where it is compared to the fractional bit portion of the pixel data. A first blue noise bit, BN(1), is generated based on this comparison. Typically, BN(1) is a “1” when the fractional portion of the pixel data exceeds the threshold value from the mask. The same threshold data is also processed by inverter (712) to produce the threshold that would be shored in an inverted form of Mask A.
    Type: Grant
    Filed: February 26, 2001
    Date of Patent: August 10, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Gregory S. Pettitt, Bradley W. Walker, Matthew John Fritz
  • Patent number: 6775793
    Abstract: A data exchange system that exchanges data between processors is provided. The system includes a host processor and a target processor. Data is exchanged by forming a data pipeline between the target processor and the host processor. The data pipeline includes a data unit on the target processor, an emulator and a device driver on the host processor. The data exchange system sends data through the data pipe line by transferring the data from a target memory on the target processor with the data unit to the emulator. The data exchange system transfers the data from the emulator to the first device driver.
    Type: Grant
    Filed: December 15, 2000
    Date of Patent: August 10, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Douglas Deao, Deborah Keil, Robert McGowan, Craig McLean, Gary Swoboda, Leland Szewerenko
  • Patent number: 6774617
    Abstract: A peak detector for detecting a peak signal includes an input circuit to input an input signal, a track and hold circuit to hold the input signal and to output the peak signal, a comparator to compare the input signal and the peak signal to generate a clock signal, and said track and hold circuit to output the peak signal in accordance with the clock signal.
    Type: Grant
    Filed: November 21, 2001
    Date of Patent: August 10, 2004
    Assignee: Texas Instruments Incorporated
    Inventor: Hajime Andoh
  • Patent number: 6775750
    Abstract: A method and apparatus is provided for operating a digital system having several processors (102, 104) and peripheral devices (106, 116) connected to a shared memory subsystem (112). Two or more of the processors execute separate operating systems. In order to control access to shared resources, a set of address space regions within an address space of the memory subsystem is defined within system protection map (SPM) (150). Resource access rights are assigned to at least a portion of the set of regions to indicate which initiator resource is allowed to access each region. Using the address provided with the access request, the region being accessed by a memory access request is identified by the SPM. During each access request, the SPM identifies the source of the request using a resource identification value (R-ID) provided with each access request and then a determination is made of whether the resource accessing the identified region has access rights for the identified region.
    Type: Grant
    Filed: May 8, 2002
    Date of Patent: August 10, 2004
    Assignee: Texas Instruments Incorporated
    Inventor: Steven D. Krueger