Abstract: A supply reference voltage circuit is coupled to an output node, a supply voltage node and a supply reference voltage node and is operable to connect the output node to the supply reference voltage node and prevent current flow through an output device coupled to the output node in response to sensing a low voltage level at the supply voltage node and a non-zero voltage at the output node. The circuit is further operable to connect the supply reference voltage node to the supply voltage node in response to the voltage at the output node being a threshold voltage above the voltage at the supply voltage node. The circuit is further operable to bypass a blocking diode in response to sensing a high voltage level at the supply voltage node.

Abstract: A circuit is designed with a matched filter circuit including a plurality of fingers (700, 702, 704) coupled to receive a data symbol. Each finger corresponds to a respective path of the data symbol. Each finger produces a respective output signal. A plurality of decoder circuits (706, 708, 710) receives the respective output signal from a respective finger of the plurality of fingers. Each decoder circuit produces a respective output signal. A joint detector circuit (1310) is coupled to receive each respective output signal from the plurality of decoder circuits. The joint detector circuit produces an output signal corresponding to a predetermined code.

Abstract: Provided is a method (500) and audio circuit (100) for reducing popping noise in a load (140, 145) connected to the audio circuit, especially during audio circuit start-up. The method applies a time varying voltage (364) to the load that has a smooth, S-shaped curve when plotted over time. The device include an integrated circuit (IC) set as a channel block (110), a load connected between the channel block and ground, a bypass control (150) connected to the channel block for producing a controlled ground reference voltage having an S-shaped curve to the channel block, a shunt control (170) controlling the voltage delivered across the load, and a ground capacitor (160) coupled between the bypass control and ground. The channel block typically includes an amplifier which supplies the output voltage across the load. The bypass circuit generally includes a bypass generator and a transistor selectively providing a charge to the ground capacitor.

Abstract: A method for optical digital signal processing, comprises configuring a plurality of binary mirrors to allow a subset of the binary mirrors to represent a range of values. The plurality of binary mirrors comprise a digital micromirror device. Light from a light source is received at the digital micromirror device. The intensity of the light is altered to represent one of the values based, at least in part, on the configuration of the subset of the binary mirrors. The altered light is transmitted from the digital micromirror device to a detector array.

Abstract: A method of forming a semiconductor circuit (20). The method forms a first transistor (NT1) using various steps, such as by forming a first source/drain region (361) as a first doped region in a fixed relationship to a semiconductor substrate (22) and forming a second source/drain region (362) as a second doped region in a fixed relationship to the semiconductor substrate. The second doped region and the first doped region are of a same conductivity type. Additionally, the first transistor is formed by forming a first gate (283) in a fixed relationship to the first source/drain region and the second drain region. The method also forms a second transistor (ST1) using various steps, such as by forming a third source/drain region (341) as a third doped region in a fixed relationship to the semiconductor substrate and forming a fourth source/drain region (342) as a fourth doped region in a fixed relationship to the semiconductor substrate.

Abstract: A one transistor one capacitor micromirror with DRAM memory cell built around a large polysilicon-to-substrate capacitor which is not susceptible to recombination of photo-generated carriers caused by illumination in the projector. This large polysilicon-to-substrate capacitor overshadows the much smaller inherent parallel depletion capacitance which is sensitive to light. The device is further 100% shielded from exposed light by metal layers and the address node is located under the center of the micromirror mirror to obtain maximum shielding of light for the smaller, light sensitive, depletion portion of the capacitance. As a result the micromirror of this invention can adequately hold the cell charge in excess of the device load time of 300 &mgr;Sec even in extremely high brightness projector applications.

Abstract: A first dielectric layer (30) and a second dielectric layer (40) are formed over an etch stop layer (20). A hardmask layer (50) is formed over the second dielectric layer and a via (62) is formed in the first dielectric layer (30) and the second dielectric layer (40). A trench (85) is formed mostly in the second dielectric layer (40) by fully or partially removing BARC from the via (62) are partially etching the trench (85) and prior to completion of the trench etch process.

Abstract: A system and method are disclosed for restricting process fluid flow within a showerhead assembly which includes a process chamber (12) with a showerhead assembly (20) disposed therein. The showerhead assembly (20) has a blocking assembly (24) disposed within the showerhead assembly (20) for restricting the flow of process fluid within the showerhead assembly (20). Restricting the flow of process fluid within the showerhead effectively restricts the flow of process fluid exiting a center portion (30) of showerhead assembly (20), directed at a substrate wafer (16) disposed within the process chamber (12).

Abstract: A semiconductor package production method containing a step in which a bond layer made of a single-layer film thermoset bond is provided on the back of a wafer on which many semiconductor devices are formed, a dicing tape is pasted onto its bond layer side, and the bond layer and the wafer are diced simultaneously in order to obtain semiconductor devices with the bond layer, and a step in which the semiconductor devices with the bond layer are detached from the dicing tape and die-attached to interposing substrates serving as bodies to which they are bonded; wherein, the aforementioned film thermoset bond contains an epoxy resin, an epoxy resin hardener, and a phenoxy resin as well as 50-80 wt % of spherical silica, and the bond layer is 100 &mgr;m or thicker. A semiconductor device made by this method and a wafer for use with this method.

Abstract: The present invention is directed to a method of forming an FeRAM integrated circuit, which includes forming a TiAlON bottom electrode diffusion barrier layer prior to formation of the bottom electrode layer in an FeRAM capacitor stack. Subsequently, when performing the capacitor stack etch, the portion of the TiAlON diffusion barrier layer not covered by the FeRAM capacitor stack is etched substantially anisotropically due to the oxygen within the TiAlON diffusion barrier layer substantially preventing a lateral etching thereof. In the above manner, an undercut of the TiAlON diffusion barrier layer under the FeRAM capacitor stack is prevented. In another aspect of the invention, a method of forming an FeRAM capacitor comprises forming a multi-layer bottom electrode diffusion barrier layer. Such formation comprises forming a TiN layer over the interlayer dielectric layer and the conductive contact and forming a diffusion barrier layer thereover.

Abstract: The disclosed method and apparatus enables the testing of multiple embedded memory arrays associated with multiple processor cores on a single computer chip. According to one aspect, the disclosed method and apparatus identifies certain rows and columns within each of the embedded memory arrays that need to be disabled and also identifies certain redundant rows and columns in the embedded memory array to be activated. According to another aspect, the disclosed method and apparatus generates a map indicating where each of the memory failures occurs in each embedded memory array. If the testing process determines that the embedded memory array cannot be repaired, then a signal is provided directly to an external testing device indicating that the embedded memory array is non-repairable.

Abstract: A processor may execute a test and skip instruction that includes or otherwise specifies at least two operands that are used in a comparison operation. Based on the results of the comparison, the instruction that follows the test and skip instruction is “skipped.” The test and skip instruction may specify that the operands used in the comparison include (1) the contents of two registers, (2) the contents of one register and the contents of a memory location, or (3) the contents of one register and a stack value. In the second mode (an operand being from memory), a register is specified in the test and skip instruction that contains a value from which a pointer may be calculated. The calculated pointer preferably points to the memory location. If a stack value is used in the execution of the test and skip instruction, the instruction may include a reference to a register that points to the top of the stack.

Abstract: A method of forming an integrated circuit including an organosilicate low dielectric constant insulating layer (40) formed of a substitution group depleted silicon oxide, such as an organosilicate glass, is disclosed. Subsequent plasma processing has been observed to break bonds in such an insulating layer (40), resulting in molecules at the surface of the film with dangling bonds. Eventually, the damaged insulating layer (40) includes silanol molecules, which results in a degraded film. The disclosed method exposes the damaged insulating layer (40) to a thermally or plasma activated fluorine, hydrogen, or nitrogen, which reacts with the damaged molecules to form a passivated surface for the insulating layer (40).

Abstract: A dynamic gain equalizer-monitor (DGEM) includes a light modulator operable to modulate one or more component wavelengths of an input optical signal. The DGEM also includes a grating operable to receive one or more modulated component wavelengths from the light modulator. The grating is also operable to combine a first portion of each of the one or more modulated component wavelengths and transmit that first portion into an output optical signal. The DGEM may also include a detector array operable to receive, from the grating, a second portion of modulated component wavelengths that are separated from the first portion by the grating. The detector array is operable to generate an electrical signal proportional to an optical characteristic associated with each of the modulated component wavelengths of the second portion.

Abstract: A method of forming an organosilicate low dielectric constant insulating layer (40) in an integrated circuit, and an integrated circuit structure having such a low-k insulating layer (40), are disclosed. In the case where the low-k dielectric material of the insulating layer (40) comprises an organosilicate glass, subsequent plasma processing has been observed to break bonds between silicon and organic moieties, either by replacing an organic group with a hydroxyl group or with hydrogen, or by leaving a dangling bond. Eventually, the damaged insulating layer (40) includes silanol molecules, which results in a degraded film. The disclosed method exposes the damaged insulating layer (40) to a silylation agent such as hexamethyldisilazane, which reacts with the damaged molecules, and forms molecules that restore the properties of the film.

Abstract: A graphing calculator (10) or other computer based teaching tool that displays inequalities on a display screen. In contrast to prior art devices, the present invention provides displays of inequalities that are mathematically correct and consistent with non-electronic display of inequalities such as textbooks and black board representations to reinforce traditional teaching methods and help the student or user to readily see and understand the mathematical concepts involved. The display methods of the present invention are particularly useful for small, low-resolution displays that are typical of handheld computers and calculators.

Abstract: A programmable delay circuit (100) maximizes processor bandwidth to external peripherals by eliminating wait state addition as the only way for satisfying timing requirements. Circuit (100) includes a programmable delay chain (102) connected to a hysteresis circuit (150). A processor control signal is fed into the programmable delay chain (102) which includes at least one switch (104-116) and at least one resistive element (118-126) connected together. A first feedback circuit (128) connects the output of the programmable delay chain (102) to the input (IN2) of the first embodiment (100) to keep the falling edge of the control signal the same without any significant added delay. The hysteresis circuit (150) which provides a stable signal connects to an output driver (180) for driving the processor control signal.

Abstract: An integrated circuit including a demodulating finger is provided for variably extracting symbols in the demodulation process of spread spectrum signals. Following the uncovering of an information channel sample stream, partial I and Q accumulations are supplied at a rate of one partial I and Q accumulation per four PN chips. A dot product operation is then performed upon these partial I and Q accumulations using a pilot estimate, and the resulting partial symbols are accumulated in a second process, where the soft symbols can be selectively supplied with a symbol period in the range from 4 to 2048 PN chips. In this manner, the symbol accumulation process can be made to work with a wide variety of information channel symbol rates. A method for partially accumulating soft symbols, both before and after the dot product operation, is also provided.

Abstract: A portable particle detection and removal system (100) that connects to a house vacuum (200). A particle sensor (106) is connected between two hoses: one (102) connected to the house vacuum (200) and one (104) for vacuuming the wafer equipment chamber. A smaller diameter hose (104) may be used for vacuuming the wafer equipment chamber. The particle sensor detects (106) incoming particles and a particle count is displayed for the operator. A modulated cleaning system (112) modulates the vacuum pressure in the second hose (104) between two vacuum pressure states.

Abstract: A sequential color display system using a white light source (202) to create a full color image projected onto an image plane (214). A dynamic filter (206), typically a series of moving dichroic filters, generates a series of primary colored light beams that are swept across the surface of a spatial light modulator (210). Light rejected by the dynamic filter (206) enters a light recycler (204) and is reapplied to the dynamic filter (206). The light recycler is typically one or more reflective surfaces, including mirrors, baffles, enclosures, lamp reflectors, TIR surfaces, or specially coated material arranged in such a way as to encourage light toward an aperture separating the light recycler (204) and the dynamic filter (206). Typically all three primary colors are produced simultaneously by the dynamic filter (206).