Patents Assigned to Texas Instruments
  • Fabricating dual voltage CMOSFETs using additional implant into core at high voltage mask
    Patent number: 6713334
    Abstract: An implant at HVGX pattern (step 102c) is provided to allow selective transistor threshold voltage Vth adjustment on the core transistors without affecting the I/O transistor threshold voltage Vt. The implant provides independently tuned either NMOS core transistors and I/O transistor Vth or PMOS core transistors and I/O transistor Vth.
    Type: Grant
    Filed: August 9, 2002
    Date of Patent: March 30, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Mahalingam Nandakumar, Youngmin Kim, Amitava Chatterjee
  • System for reducing segregation and diffusion of halo implants into highly doped regions
    Patent number: 6713360
    Abstract: The present invention provides a method for forming a transistor junction in a semiconductor wafer by implanting a dopant material (116) into the semiconductor wafer, implanting a halo material (110) into the semiconductor wafer (102), selecting a fluorine dose and energy to tailor one or more characteristics of the transistor, implanting fluorine into the semiconductor wafer at the selected dose and energy, activating the dopant material using a thermal process and annealing the semiconductor wafer to remove residual fluorine. The one or more characteristics of the transistor may include halo segregation, halo diffusion, the sharpness of the halo profile, dopant activation, dopant profile sharpness, drive current, bottom wall capacitance or near edge capacitance.
    Type: Grant
    Filed: August 12, 2002
    Date of Patent: March 30, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Amitabh Jain, Kaiping Liu, Zhiqiang Wu
  • Lead over chip semiconductor device including a heat sink for heat dissipation
    Patent number: 6713851
    Abstract: The invention relates to an LOC type semiconductor device having improved heat radiation. The semiconductor device related to the present invention has a preferably metal heat-radiating element 7 that is in thermal contact with the surface opposite the principal surface of the semiconductor chip 3. One region of said heat-radiating element 7 is externally exposed from the package that encloses the semiconductor chip 3. The heat-radiating element 7 is in thermal contact with a metal pattern 12 that is formed on the substrate 10 on which the semiconductor device is mounted. The heat from the semiconductor chip is transferred to the mounting substrate 10 side via the heat-radiating plate 7, and heat dissipation is conducted efficiently.
    Type: Grant
    Filed: September 2, 1999
    Date of Patent: March 30, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Norito Umehara, Masazumi Amagai
  • Semiconductor device and method of manufacturing same
    Patent number: 6713881
    Abstract: Object: To provide sufficient connection strength between the bonding pads and conductor wires in a wire bonding method. Means for Solution: The bonding pads 20 upon a semiconductor chip 18 are provided with a bonding region 30 and a probe contact region 32, and one end of the conductor wire 22 is bonded to the bonding region 30. The probe contact to the probe contact region 32 is used for making contact to the tips of the test probes in the semiconductor chip inspection step performed prior to the bonding.
    Type: Grant
    Filed: May 25, 2001
    Date of Patent: March 30, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Norito Umehara, Yoshikatsu Umeda
  • Apparatus and method for a sorting mode in a direct memory access controller of a digital signal processor
    Patent number: 6715058
    Abstract: In order to sort signal group elements organized in blocks in a time-division multiplex protocol into frames of related elements, an address unit addresses the first element in each of the element blocks, then the second element in each element block, etc until all of the elements of all of the blocks have been addressed. In this manner, the related elements are sorted into frames of elements. The address unit performs this element sorting using a base address, an element index equal to the number of elements in a block, and a frame index equal to {the number of elements times (the number of frames minus one)} minus one as parameters.
    Type: Grant
    Filed: September 27, 2000
    Date of Patent: March 30, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Patrick J. Smith, Tai H. Nguyen
  • Housing and internal layout for compact SLM-based projector
    Patent number: 6712475
    Abstract: A display system based on a spatial light modulator (SLM). Various embodiments of the invention all involve some sort of articulating element, such that the display system has a stow position that is more compact and different from its operating position. In the operating position, the image formed by the SLM is re-oriented, if necessary, to a position suitable for viewing.
    Type: Grant
    Filed: August 31, 2001
    Date of Patent: March 30, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Michael T. Davis, John T. McKinley
  • System and method for converting a DC input voltage to a DC output voltage
    Patent number: 6713676
    Abstract: A system for converting a DC input voltage to a DC output voltage includes at least one integrated circuit die electrically coupled to a leadframe. An inductor is also coupled to the leadframe and electrically coupled to the integrated circuit die. An inductor casing generally surrounds the inductor, and a molding encapsulates the integrated circuit die, a portion of the leadframe, and a portion of the inductor. The integrated circuit die and the inductor are operable to receive the direct current input voltage and to convert the direct current input voltage to the direct current output voltage.
    Type: Grant
    Filed: November 14, 2001
    Date of Patent: March 30, 2004
    Assignee: Texas Instruments Incorporated
    Inventor: Klaus Fischer
  • MEM's mirror internal sensor linearization based on driver linearity
    Patent number: 6714338
    Abstract: A technique that reduces or eliminates the non-linearities associated with the internal feedback sensor used in a micro-electro-mechanical mirror assembly. Using the relatively linear response of the mirror positioning motor, associated driver electronics, and the mirror itself, a calibration is performed that compensates for the internal feedback sensor non-linearity. An expected position can then be calculated simply by multiplying the gain of the system by the output, due to the good inherent linearity in the system. The calibration will compare measured versus expected position criteria for a predefined set of constant outputs. The data will form a look-up table that will be used to correct for the sensor non-linearities.
    Type: Grant
    Filed: May 16, 2002
    Date of Patent: March 30, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Eric G. Oettinger, Mark D. Heminger, Mark D. Hagen
  • Circuit assembly for producing a one-way connection between transmitter and/or receiver units and an antenna
    Patent number: 6714766
    Abstract: In a circuit assembly for producing a one-way connection between a first transmitter or receiver (12) operating on a first frequency and an antenna (16), on the one hand, as well as between a second transmitter or receiver (14) operating on a second frequency and the antenna (16) on the other, each transmitter or receiver having a port for producing a connection to the antenna (16) a filter (18) is used having at least one symmetrical port, the passband of which covers the first and the second frequency, whereby the antenna (16) is connected to one of the ports of the filter (18). A first passive network (24) between one lead of the at least one symmetrical port of the filter (18) and the input of the first transmitter or receiver (12) short-circuits at the second frequency the port (20) of the first transmitter or receiver (12).
    Type: Grant
    Filed: October 11, 2000
    Date of Patent: March 30, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Thomas Keller, Manfred Plankensteiner
  • Method for screening semiconductor devices for contact coplanarity
    Patent number: 6713311
    Abstract: A method for determining contact coplanarity of packaged semiconductor devices having a plurality of contacts. The method includes the steps of measuring the relative positions of the contacts on a subject semiconductor device; calculating from the measurements seating planes 64 formed by tilting the device to one or more of its corners and/or sides such that each said plane comprises contacts at or adjacent to the corners of the device; using the measured relative contact positions and the calculated seating planes to determine the highest deviation from contact coplanarity for the semiconductor device.
    Type: Grant
    Filed: September 25, 2001
    Date of Patent: March 30, 2004
    Assignee: Texas Instruments Incorporated
    Inventor: Lik Son Wong
  • Semiconductor leadframes plated with thick nickel, minimum palladium, and pure tin
    Patent number: 6713852
    Abstract: A leadframe for use with integrated circuit chips comprising a base metal having a plated layer of nickel fully covering said base metal; a plated layer of pure tin on said nickel layer, selectively covering areas of said leadframe intended for attachment to other parts; and a plated layer of palladium on said nickel layer, selectively covering areas of said leadframe intended for bonding wire attachment.
    Type: Grant
    Filed: February 1, 2002
    Date of Patent: March 30, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Donald C. Abbott, Douglas W. Romm
  • Method and structure for controlling surface properties of dielectric layers in a thin film component for improved trimming
    Publication number: 20040056326
    Abstract: A method and structure for controlling the surface properties in the dielectric layers in a thin film component can be provided for improving the trimming process of thin film element. A metal fill is configured with a uniform fill pattern beneath an array of thin film resistors, and can comprise a plurality of smaller features or peaks providing a finer fill pattern that improves the control of the topology of the dielectric layers. The fill pattern can be configured in various manners, such as fill patterns parallel to the thin film resistor, fill patterns perpendicular to the thin film resistor, or fill patterns comprising a checkerboard-like configuration.
    Type: Application
    Filed: September 20, 2002
    Publication date: March 25, 2004
    Applicant: Texas Instruments Incorporated
    Inventors: Eric W. Beach, Walter B. Meinel, Eric L. Hoyt
  • System and method to automatically stack and unstack java local variables
    Publication number: 20040059893
    Abstract: A processor preferably comprises a processing core that generates memory addresses to access a memory and on which a plurality of methods operate, a cache coupled to the processing core, and a programmable register containing a pointer to a currently active method's set of local variables. The cache may be used to store one or more sets of local variables, each set being used by a method. Further, the cache may include at least two sets of local variables corresponding to different methods, one method calling the other method and the sets of local variables may be separated by a pointer to the set of local variables corresponding to the calling method.
    Type: Application
    Filed: July 31, 2003
    Publication date: March 25, 2004
    Applicant: Texas Instruments Incorporated
    Inventors: Gerard Chauvel, Maija Kuusela, Dominique D'Inverno
  • Method for improving gate oxide integrity and interface quality in a multi-gate oxidation process
    Patent number: 6709932
    Abstract: One aspect of the invention relates to a method of manufacturing a multi-gate integrated circuit device. According to the method, a protective coating substantially prevents processes used to form a second gate dielectric from affecting a first gate dielectric. In an exemplary process, an oxide gate dielectric is grown for peripheral region transistors, a protective coating of silicon nitride is deposited over the peripheral region gate oxide, the oxide and protective coating are etched from a core region, and then a second oxide dielectric is grown for core region transistors while the silicon nitride coating substantially prevents further oxide growth in the peripheral region. The protective coating can also prevent nitridation of the core region gate dielectric from affecting the peripheral region gate dielectric.
    Type: Grant
    Filed: August 30, 2002
    Date of Patent: March 23, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Anand T. Krishnan, Vijay Reddy
  • Bipolar class AB folded cascode operational amplifier for high-speed applications
    Patent number: 6710654
    Abstract: The present invention (800) comprises an operational amplifier with a first stage comparator circuit (801) for biasing a second stage folded cascode amplifier circuit (802). The result is that the input differential voltage signal to output current signal is transformed from a tanh function to a sinh function. The present invention provides the low noise, low distortion, high gain, wide bandwidth and good DC performance characteristics of the folded cascode op-amp configuration, with much improved slew rate.
    Type: Grant
    Filed: November 15, 2001
    Date of Patent: March 23, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Charles Parkhurst, Julio E. Acosta
  • Source/drain extension fabrication process with direct implantation
    Patent number: 6709938
    Abstract: An improved source/drain extension process is provided by the following processing steps of implanting NMOS devices directly on either side of the gates without an oxide layer (step D2), covering the gates with a cap oxide layer(step E2), covering NMOS devices with photoresist(step F2), dry etching all PMOS devices (Step G2), and implanting PMOS devices (step I2).
    Type: Grant
    Filed: July 18, 2002
    Date of Patent: March 23, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Donald S. Miles, Douglas T. Grider, P. R. Chidambaram, Amitabh Jain
  • Data processor with flexible multiply unit
    Patent number: 6711602
    Abstract: An embodiment of the invention includes a pair of parallel 16×16 multipliers each with two 32-bit inputs and one 32-bit output. There are options to allow input halfword and byte selection for four independent 8×8 or two independent 16×16 multiplications, real and imaginary parts of comple×multiplication, pairs of partial sums for 32×32 multiplication, and partial sums for 16×32 multiplication. There are options to allow internal hardwired routing of each multiplier unit results to achieve partial-sum shifting as required to support above options. There is a redundant digit arithmetic adder before final outputs to support additions for partial sum accumulation, complex multiplication vector accumulation and general accumulation for FIRs/IIRs—giving MAC unit functionality. There are options controlled using bit fields in a control register passed to the multiplier unit as an operand.
    Type: Grant
    Filed: October 31, 2000
    Date of Patent: March 23, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Amarjit Singh Bhandal, Keith Balmer, David Hoyle, Karl M. Guttag, Zahid Hussain
  • Aircraft circuit breaker with manual opening resistant feature
    Patent number: 6710695
    Abstract: A pushbutton resettable circuit breaker is shown having features to prevent manual opening by simply pulling outwardly on the pushbutton. In one embodiment, the pushbutton (16) is formed with slots (16b) which are configured to provide a reaction surface essentially inaccessible without a special purpose contact opening tool (30). The tool is provided with portions that are insertable into the slots and into engagement with the reaction surfaces for pulling the pushbutton out and manually opening the contacts. In a second embodiment, a small aperture 16k is formed through the rating tab and top and wall of the button and in alignment with a movable plunger (28). A special purpose contact opening tool (32, 34) can be inserted through the aperture to apply a force to the plunger and mechanically trip the circuit breaker.
    Type: Grant
    Filed: October 24, 2002
    Date of Patent: March 23, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Christian V. Pellon, Karen M. Litwin, Roland G. Morin, Peter G. Berg
  • Digital control loop to solve instability of electrostatic drives beyond ⅓ gap limit
    Patent number: 6710507
    Abstract: A circuit (40) and method are provided to create a drive voltage that is linearly proportional to a position of a movable member (12) of an electrostatic actuator device (10) that is positioned by a voltage (18) applied thereto. The circuit (40) has a sensor (42) to sense a position of the movable member (12) from a reference position (d0) to provide an analog position indicating signal. An analog-to-digital converter (ADC) (46) receives the analog position indicating signal and converts it to a digital position indicating signal. A digital signal processor (DSP) (48), programmed to convert the digital position indicating signal into a digital signal that is linearly proportional to the position of the movable member, receives the digital position indicating signal.
    Type: Grant
    Filed: January 7, 2002
    Date of Patent: March 23, 2004
    Assignee: Texas Instruments Incorporated
    Inventor: Terence J. Murphy
  • Process for manufacturing a two-axis mirror
    Patent number: 6709948
    Abstract: A process for manufacturing a wafer from a layer of material such as silicon and having a multiplicity of MEMS devices such as mirrors with gimbals formed thereon is disclosed. The features of the devices on the wafer as well as the boundaries which separate individual devices are defined by lines having a constant width so as to avoid microloading effects. Waste areas of the layer of material which are greater than the constant line width are removed as breakout pieces during the release process.
    Type: Grant
    Filed: May 15, 2002
    Date of Patent: March 23, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Andrew S. Dewa, John W. Orcutt, David Ian Forehand