Abstract: A system for determining a position error in a wafer handling device includes a control module, an image acquisition module, and an image analysis module. The control module moves a workpiece having one or more reference marks, and the image acquisition module captures an image of at least one reference mark. The image analysis module, which is coupled to the image acquisition module, compares the captured image to stored target information to determine a position error.

Abstract: A comparator includes a differential amplifier stage comprising two emitter-interconnected bipolar transistors whose bases form the two inputs of the comparator, a first load element connected to the collector of the first bipolar transistor and a second load element connected to the collector of the second bipolar transistor. The comparator also includes a first MOSFET and a second MOSFET, a circuit point at which the drop in voltage across the first load element in operation of the differential amplifier stage occurs is connected to the source of the first MOSFET and the backgate of the second MOSFET, the circuit point at which the drop in voltage across the second load element in operation of the differential amplifier stage being connected to the source of the second MOSFET and the backgate of the first MOSFET, and the drain of the second MOSFET forming the output of the comparator.

Abstract: A port fitting is formed with a closed, pedestal end forming a diaphragm on which a strain gauge sensor is mounted. A support member is received on the pedestal end and is formed with a flat end wall having an aperture aligned with the sensor. A portion of a flexible circuit assembly is bonded to the flat end wall with a connector disposed over the support member. A tubular outer housing is fitted over the several components and its bottom portion is welded to the port fitting while its top portion places a selected load on an O-ring received about the connector as well as internal components of the transducer. In one embodiment, a loading washer (72a) is disposed over the O-ring on a first portion (70a) of a two portion connector (70) and retained by a second connector portion (70b). Protrusions (76a1) formed on the tubular housing (76) pass through cut-outs in the second connector portion to place a load on the loading washer.

Abstract: A method of forming two regions having differing depths using a single implantation process is provided. A mask having two openings associated therewith is formed over a semiconductor body, wherein one of the openings has a size larger than an implantation design rule, and the other opening has a size smaller than the design rule. An implant is performed into the semiconductor body through the implant mask, resulting in two distinct doped regions, wherein the region associated with the larger opening has more dopant than the region associated with the smaller opening. Subsequent activation and thermal processing results in the one region diffusing a greater amount than the second region, thereby resulting in two regions formed concurrently having different depths.

Abstract: A system for measuring signals in a non-linear network is provided which reduces the reliance on hardware and processing support when correcting for A/D offset by performing a pair of dual slope measurement cycles with an integrating analog to digital converter (ADC) circuit. Each of the measurement cycles has at least four phases including a first integrating phase and a first de-integrating phase followed by a second integrating phase and a second de-integrating phase. The system further includes an ADC controller operatively communicative with the integrating ADC circuit for detecting when the first count value is reached during the second de-integrating phase and then resetting the second count value in response to this detection so that the second count value is offset corrected at the end of the second de-integration phase. As a result, a difference calculation is automatically performed during the measurement cycle.

Abstract: A high-frequency compatible bidirectional level conversion circuit in which high-voltage port A and low-voltage port B are connected using pass transistor 12, and the side of port A is connected to power supply voltage terminal C using primary and secondary switching circuits 21 and 22 connected in parallel. When port B changes from low level to high level to transmit a level-converted signal from the side of port B to the side of port A, the level at port A rises to turn on primary and secondary switching circuits 21 and 22, and secondary switching circuit 21 turns off after port A has reached the high level. When secondary switching circuit 22 is configured to have a lower impedance than that of primary switching circuit 21, the load capacitance connected to port A is charged by a high current which flows in secondary switching circuit 22 as the level of port A rises. When port B changes from the high level to the low level, secondary switching circuit 22 remains off.

Abstract: The present invention comprises a low cost device (10, 20) and a method (30) of forming an electrical interconnect between two metal substrate layers configured in a flip-chip format or a wire bonded format. The invention includes a first metal substrate layer (12), a second metal substrate layer (14), and an organic tape layer (16) attached therebetween as a dielectric. The organic tape layer (16) includes a series of spaced apart vias (15) adapted to receive solder paste (13). The second metal layer (14) includes a plurality of openings (40,42,44) spaced along the surface thereof and coaxially aligned with the spaced vias (15). Further, the invention includes a plurality of solder balls (17, 18, 19) placed across the respective openings (40,42,44) of the second metal layer (14) such that each solder ball (17-19) attaches to the solder paste (13) forming an electrical interconnect running substantially in parallel between the metal layers (12, 14).

Abstract: An interpoly dielectric is formed using only a single layer of oxide and a single layer of nitride to allow a reduction in thickness. The nitride is thermally grown on silicon in a nitrogen environment to maintain a high quality layer, while the oxide is deposited by LPCVD.

Abstract: Techniques which allow a bit value stored/generated by integrated circuits to be changed by changing potentially only one of several masks used to fabricate the circuits. For example, when a single mask is to be re-designed to implement a design change (e.g., to fix minor bugs) and a version identifier is to be changed, the same mask can be used to implement the change in the version identifier as well. An embodiment allows the bit value to be changed any number of times by changing only one mask. As a result, the invention minimizes the number of masks that may need to be changed when implementing design changes.

Abstract: A launch multiplexor which enables a desired bit to be stored into a desired memory element when using sequential scanning techniques (e.g., automatic test pattern generation (ATPG)). The launch multiplexor may be employed in addition to a scan multiplexor, which enables the test pattern bits or normal operating input to be selected and stored in the desired memory element. The scan multiplexor is used to scan-in a test pattern and evaluate a first input, and the launch multiplexor provides the control to store a desired bit into the corresponding memory element. Another output may be evaluated after storing the desired bit. In an embodiment, launch multiplexors are used associated with only memory elements in the critical paths, and the delay in transitioning from one output to another may be conveniently measured.

Abstract: According to one embodiment of the invention, a method for manufacturing bipolar junction transistors includes disposing a first oxide layer between a semiconductor substrate and a base polysilicon layer, forming a dielectric layer outwardly from the base polysilicon layer, and forming an emitter region by removing a portion of the dielectric layer and a portion of the base polysilicon layer. The method further includes removing a portion of the first oxide layer to form undercut regions adjacent the emitter region and to enlarge the emitter region, and forming an oxide pad outwardly from the semiconductor substrate in the emitter region.

Abstract: A packaged micromirror assembly (21, 21′) is disclosed. The assembly (21, 21′) includes a mirror element (41) having a mirror surface (29) that can rotate in two axes. Magnets (53) are attached to the mirror element (41), to permit rotation of the mirror surface (29) responsive to the energizing of coil drivers (36). A sensor (63, 80) is disposed under the mirror surface (29) to detect mirror orientation. In one aspect of the invention, the sensor (63) includes a light source such as an LED (68) that imparts light through an aperture (66) at the underside of the mirror surface (29). Light detectors (65) are arranged at varying angles, and detect relative intensity of light reflected from the underside of the mirror surface (29), from which the rotational position of the mirror (29) can be derived. According to another aspect of the invention, a conical sensor (80) with multiple insulated segmented capacitor plates are arranged under the mirror surface (29).

Abstract: An improved high performance scheme is provided with a serial peripheral interface (SPI) to enable microcontroller-based products and other components and devices to achieve a higher serial transmit and receive data rate. An exemplary technique utilizes a CPU and an SPI having a circular FIFO structure. To prevent the memory traffic associated with any SPI accesses from conflicting with other CPU memory accesses, the technique utilizes cycle stealing direct memory access techniques for SPI data transfers with the memory. During a CPU read/write sequence, data is read/written from/to the memory through a virtual special function register (SFR). Once the virtual SFR access is detected, all accesses are redirected to the circular FIFO buffer memory, with no additional pipelining necessary. The CPU pointers can suitably increment as appropriately controlled by hardware.

Abstract: An integrated semiconductor circuit (10) with function inputs (14a) and function outputs (16a), as well as with function units (12), which supply the function outputs (16a) with output signals which they generate as a function of the input signals applied to the function inputs (14a), including test inputs (18) and test outputs (20), as well as an interface unit (22, 26) which is inserted between the function units (12), on the one hand, and some of the function inputs (14a) and some of the function outputs (16a). The interface unit (22, 26) can be switched over, by means of test control signals applied to it, in such a way that it connects these several function inputs (14a) to the test outputs (20) or to the function units (12), and these several function outputs (16a) to the test inputs (18) or to the function units (12).

Abstract: The present invention is directed to a method of forming an FeRAM integrated circuit, which includes forming a sidewall diffusion barrier prior to etching the bottom electrode diffusion barrier layer. The sidewall diffusion barrier layer is then etched prior to the bottom electrode diffusion barrier layer. In patterning an AlOx sidewall diffusion barrier layer prior to etching the underlying bottom electrode diffusion barrier layer, the etch chemistry comprises BCl3+Ar. The BCl3 is effective in etching the AlOx with a good selectivity to the underlying nitride hard mask on top of the capacitor stack (e.g., TiAlN) and nitride bottom electrode diffusion barrier (e.g., TiAlON with small oxygen content) between the neighboring capacitor stacks. The Ar may be added to the etch chemistry because the resulting surface (of a top portion of the hard mask and the bottom electrode diffusion barrier) is smoother.

Abstract: Cleaning methods are disclosed for removing sidewall polymers from interconnect vias or trenches, wherein a wafer is exposed to a plasma comprising hydrogen and an inert gas in a plasma cleaning chamber following etch-stop etching.

Abstract: An audio amplifier output stage layout technique achieves minimum cross coupling between audio amplifier channels. Regarding TDAA output stages, the typical TDAA includes two demodulation inductors per audio channel. The two pair of demodulation inductors associated with the TDAA are arranged to form an X-pattern to simultaneously minimize cross coupling between audio amplifier channels and reduce PCB layout size.

Abstract: A method and circuit for measuring a charge distribution for readout from a memory such as a FeRAM uses on-chip compression of bit line voltage measurements. One embodiment includes a compression circuit coupled to sense amplifiers. Each sense amplifier compares a series of reference voltages to a corresponding bit line and sets a result value for the comparison. A series of result values from a sense amplifier has a transition when the bit line voltage is approximately equal to the reference voltage. The compression circuit can use the transition as a trigger to record a compressed value indicating the reference voltage at the transition.

Abstract: The present invention facilitates semiconductor cooling by combining a semiconductor die and a thermoelectric cooler into a single, integrated package or system. The thermoelectric cooler is controllably operated so as to dissipate thermal energy generated by the semiconductor die. Active thermal management of the package is performed by a controller, which monitors temperature(s) of the semiconductor die and increases or adjusts cooling such that desired performance levels can be obtained. The invention can also thermally manage one or more regions of a semiconductor die and can thermally manage a plurality of semiconductor dies.

Abstract: Antenna reception diversity is provided for wireless communications such that a received signal (r) can be produced by combining antenna signals (vi) with their associated fading amplitudes (&agr;i) as estimated by a linear receiver (32). Also, antenna signals (v1i) can be combined with their associated correlation values (&agr;1i) in place of estimated fading amplitudes. Further, inherent characteristics of a non-linear wireless communication receiver can be exploited such that a received signal (r2, r3) can be produced without any additional overhead that would otherwise be needed to provide estimated fading amplitudes.