Abstract: Methods and compositions are disclosed for chemical mechanical polishing (CMP) of semiconductor substrates, post-CMP storage of semiconductor substrates and post-CMP cleaning of semiconductor substrates. The methods and compositions feature the use of surfactants and, in some cases, passivation agents. The methods and compositions are particularly suited to polishing, storing and cleaning semiconductor substrates comprising hydrophobic surfaces.

Abstract: In some embodiments, a system comprises a processor that executes an algorithm. Coupled to the processor is memory that stores the algorithm. In addition, the system comprises a hardware unit that is generally not accessible to the algorithm and an abstraction layer that indirectly facilitates interaction between the hardware unit and the algorithm. The hardware unit comprises one or more physical resources, such as data channels, that are associated by the abstraction layer with a logical resource. In addition, the abstraction layer creates an identifier to the logical resource that may be used by the algorithm. Associated with the identifier is a private state that represents the most recently configured settings of the logical resource. A vector table is used in conjugation with the private state to identify memory locations of optimized command functions that carry out operations associated with the hardware unit. In addition, the vector table is adapted to reflect the run-time state of the system.

Abstract: A processor (e.g., a co-processor) comprising a decoder coupled to a pre-decoder, in which the decoder decodes a current instruction in parallel with the pre-decoder pre-decoding a subsequent instruction. In particular, the pre-decoder examines at least five Bytecodes in parallel with the decoder decoding a current instruction. The pre-decoder determines if a subsequent instruction contains a prefix. If a prefix is detected in at least one of the five Bytecodes, a program counter skips the prefix and changes the behavior of the decoder during the decoding of the subsequent instruction.

Abstract: A test system is disclosed in which the packet error rate of a wireless card can be determined without having knowledge of the software interface to the card. The wireless card under test is placed inside an anechoic chamber. Test equipment emulates an access point and the card under test “associates” itself with the emulated access point. The test equipment includes an arbitrary waveform generator, RF signal generator, and a controller which emulates an access point. The controller commands the arbitrary waveform generator and RF signal generator to transmit a test data packet to the card under test. If the test data packet is correctly received by the test card, the card transmits back an acknowledgment packet. The controller computes the packet error rate based on the number of lost packets relative to the total number of test data packets sent.

Abstract: A cache subsystem may comprise a multi-way set associative cache and a data memory that holds a contiguous block of memory defined by an address stored in a register. Local variables (e.g., Java local variables) may be stored in the data memory. The data memory preferably is adapted to store two groups of local variables. A first group comprises local variables associated with finished methods and a second group comprises local variables associated with unfinished methods. Further, local variables are saved to, or fetched from, external memory upon a context change based on a threshold value differentiating the first and second groups. The first value may comprise a threshold address or an allocation bit associated with each of a plurality of lines forming the data memory.

Abstract: Methods and compositions are disclosed for chemical mechanical polishing (CMP) of semiconductor substrates, post-CMP storage of semiconductor substrates and post-CMP cleaning of semiconductor substrates. The methods and compositions feature the use of surfactants and, in some cases, passivation agents. The methods and compositions are particularly suited to polishing, storing and cleaning semiconductor substrates comprising hydrophobic surfaces.

Abstract: The invention discloses a method for attaching solder members (114) to a substrate (112). The method includes forming a decal (110) with a plurality of solder members (114). The method further comprises aligning the decal (110) with the substrate (112) and transferring the solder members (114) on the decal (110) to the substrate (112).

Abstract: An integrated circuit constructed for easy debug and emulation includes a function clock circuit and an operation circuit operating in synchronism with a function clock. A trace trigger circuit triggers trace operation upon detection of a predetermined condition within the operation circuit. A FIFO buffer receives the trace data which is exported via a trace port. The integrated circuit includes an oscillator clock circuit which may be synchronized with the function clock or a reference clock. The oscillator clock circuit operates in several modes selected by an externally writeable control register. The clock circuit synchronizes with the function clock signal or a reference clock signal as selected by the control register. Pre-scalers are employed in two paths to scale the oscillator clock frequency. The clock circuit also includes calibration and test modes selected by the control register.

Abstract: An integrated circuit that includes a high breakdown voltage bipolar transistor. The bipolar transistor includes an emitter 36, a base 32, and a collector structure. The emitter 36 is adjacent to and overlies the base 32 and the base 32 is adjacent to and overlies a core portion 48 of the collector structure. The collector structure includes, in addition to the core portion 48, a collector contact region 31 and a lateral collector region 50 between the core portion 48 and the collector contact region 31. The lateral collector region 50 is thinner than said collector contact region at some point along its length.

Abstract: A MOSFET structure with silicate gate dielectrics and silicon or metal gates with HF-based wet silicate gate dielectric etch.

Abstract: A differential circuit to read differential data from a disk by a current bias on a plurality of read heads includes a read circuit to read the differential data from the disk by maintaining the current bias. The current is below a maximum current of a read head having the lowest maximum voltage of said plurality of read heads.

Abstract: A vertical bipolar transistor having low breakdown voltage, low ESD clamping voltage and high beta is fabricated in a semiconductor 301 of a first conductivity type, which has a buried layer 360 of the opposite conductivity type with sharp junctions, suitable as collector. This layer extends laterally to deep wells 371 of the opposite conductivity type, thus isolating the subsurface band 301a of the semiconductor of the first conductivity type. This band is suitable as the base and has a width 301c controlled by the proximity of the buried layer junction 360a. The emitter 310 is supplied by a surface region of the opposite conductivity type. The photomask, which is needed for implanting the low energy ions to create the extended emitter, is also used for the process step of implanting, at high energy and high dose, the ions needed (opposite conductivity type) to create the buried layer.

Abstract: The addition of a specialized instruction to perform the MAX star function provides a way to get better performance turbo decoding on a digital signal processor. A subtractor forms the difference between inputs A and B. The sign of this difference controls a multiplexer selection of the max function maximum of inputs A and B. The difference is applied to a lookup table built to handle both positive and negative inputs. The look up table output is summed with with the difference to form the MAX star result. The size of the lookup table is selected to match the required resolution.

Abstract: A system and method of providing a micromirror pixel 400 that is highly resistant to bright failure states. The micromirror 400 uses an asymmetric yoke 402 to ensure the mirror is only attracted to the address electrode in one rotation direction. The landing mechanism on the other side of the torsion binge axis also is altered to allow the pixel to over rotate in the “off” direction. The over rotation ensures that light reflected by the mirror when in the off direction will miss the projection lens pupil, allowing the corresponding pixel to remain dark in both an operational and failed state.

Abstract: A ferroelectric memory structure is described for the 1T1C arrangement in a ferroelectric capacitor cell array for FeRAM memory device applications. The device structure provides an accurate reference voltage and a simple sensing scheme for the sense amplifier used for reading the state of a target memory cell of the FeRAM array. A reference circuit generates a reference voltage which is a function of a charge shared between a plurality of FeRAM dummy cells. Each dummy cell of the plurality of FeRAM dummy cells is selectively coupleable to a plurality of bitlines. A shorting transistor in the reference circuit couples two bitlines or two bitline-bars neighboring the selected target memory cell. One dummy cell is coupled to a select one of the two shorted bitlines or bitline-bars, and another dummy cell is coupled to a another of the two shorted bitlines or bitline-bars, wherein at least one dummy cell is biased to a “0” state, and at least one other dummy cell is biased to a “1” state.

Abstract: An improved interference cancellation technique is disclosed. Digital baseband circuitry (40) includes user and symbol detection circuitry (50) for performing a Gibbs sampler type of interference cancellation, either embodied in custom hardware (44) or in software. Random initial guesses for a signal sample (either a symbol or chip) are made for each user. Interference cancellation is performed on a user-by-user basis, using the then-current data decision values for the other, interfering users. A soft data decision is used to derive a probability distribution function for the actual data decision for the sample for the user. A randomly selected value is applied against the probability distribution function to generate the next data decision value for that user, and the process is repeated until convergence. Following convergence, a statistic is used to select a final data decision value for each user, from the set of intermediate data decision values stored in memory.

Abstract: An electronic device may receive a packet comprising a plurality of codewords comprising pre-processing logic, a first decoder, and a second decoder. The pre-processing logic causes some of said codewords to be provided to the first decoder and other of said codewords to be provided to the second decoder. The codewords may be of different lengths and/or different code rates. Further, the first and second decoders may implement the same or different decoding technique.

Abstract: A method for fabricating a body contact silicon-on-insulator transistor (10) includes forming a semiconductor substrate (12) over an insulator (14) and lightly doping the semiconductor substrate (12) to form a body region (18). The method also includes forming a gate (20) over the semiconductor substrate (12) and separated from the semiconductor substrate (12) by a gate insulator layer (21). The gate (20) defines a source region (22), a drain region (24) and a contact region (26). The method also includes masking a portion (36) of the gate (20) and the contact region (26) and heavily doping the source region (22), the drain region (24) and an unmasked portion (36) of the gate (20) with a material having a conductivity substantially opposite a conductivity of the body region (18).

Abstract: A device measures air flow at multiple points in an air channel. The device includes a metering plate that has multiple passages through the metering plate. The metering plate is adapted to be positioned across the air channel in an orientation that places two or more of the multiple passages at two or more respective locations within the air channel. The metering plate is also adapted to receive two or more flow meters at the two or more passages, respectively. In addition, the metering plate is configured so that respective air flow velocities at the two or more locations when the metering plate is positioned across the air channel substantially matches air flow velocities at the two or more locations when the metering plate is not positioned across the air channel. An example embodiment includes holders such as sockets that keep the flow meters fixed in the metering plate with regard to pitch and roll.

Abstract: A method for processing semiconductor wafers includes processing a semiconductor wafer in a processing chamber having upper and lower chambers, decoupling the upper chamber from the lower chamber, cleaning the upper chamber, determining, while decoupled, that a leak rate and a particle count for the upper chamber meets predetermined criteria, and coupling the upper chamber to the lower chamber.