Abstract: A method for performing audible fast-forward or reverse of audio content represented in a compressed format, such as, but not limited to, MPEG-1 Layer 3 (MP3) or MPEG-2 Advance Audio Coding (AAC) employs a fast-forward controller which performs fast-forward or reverse by repeatedly skipping forward or reverse in the compressed audio data stream, retrieving a block of data, and then splicing these data blocks back together. A decoder is then used to decode each of these blocks, to detect when a block switch has occurred (a splice in the data stream), and to quickly resynchronize at each transition. Hierarchical or multiplexed data streams may be decoded using a cascade of decoders each employing this technique. The decoder uses a robust sync search for performing resynchronization and error recovery.

Abstract: A system and method are provided for controlling operation of an actuator for retracting a read/write head of a hard disk drive system. One aspect of the system and method relates to controlling the actuator in response to a retract request command by first decelerating the actuator for a time period and then braking of the actuator for another time period. Another aspect of the system and method relates to controlling operation of the actuator during retract based on a sensed back EMF relative to a target back EMF, which may be selected by a user.

Abstract: A digital multiplier 110 for multiplying a plurality of multiplicand signals X0-X23 representing a multiplicand and a plurality of multiplier signals Y0-Y23 representing a multiplier. In it, a plurality of intermediate results signals, such as partial product signals, are generated from the multiplicand signals and the multiplier signals. A plurality of adder circuits 40 are also provided for adding the intermediate results signals to generate a plurality of final result signals representing the result of multiplying the multiplicand and the multiplier, wherein at least some of the adder circuits receive first signals representing intermediate addition results from at least two prior adder stages and also receive second signals representing intermediate results generated as the result of only a single addition.

Abstract: A three-phase motor protector uses two toroids to monitor all three phases of a three-phase motor. Current and phase loss are monitored directly in phases A and B while the phase C current level is determined by analysis of the phase A and B relationship. Current is induced into the phase A and B toroids from the motor supply lines with the resulting wave fed to an input of high-gain inverting amplifiers to provide A and B square waves which are inputted to separate channels of a microprocessor (U3). The square waves are processed by an AND gate providing an output square wave with a 16.66 percent duty cycle for normal operation. Upon loss of phase C the ANDed result is a digital low since the individual waves of phases A and B become an inverse of one another. In order to prevent nuisance tripping an AND output of less than 2 percent duty cycle is treated as a phase loss.

Abstract: Methods are disclosed for reading data from memory cells such as a ferroelectric memory cell in a memory device, where one sense amp bitline is coupled with a precharge voltage while another sense amp bitline is coupled with the memory cell.

Abstract: A thermally compensated circuit breaker has a movable contact assembly (24) which mounts a movable electrical contact (24m) for movement between open and closed contacts positions with a stationary electrical contact (26). The contacts are maintained in the closed circuits position by a latching mechanism (24b, 28g) which prevents opening of the contacts through an opening contacts force provided by a spring (24e). A current carrying trip arm (40a, 44a) deflects upon sufficient I2R heating to transfer motion to the latch to separate the latch (24b) from the latch receiving catch (28g) to trip the circuit breaker. The trip arm (40a, 44a) is part of a pivotably mounted actuator assembly (40, 44) having a movable end portion spaced from the pivot disposed adjacent a motion transfer member (28c). A calibration screw (42a) is located so that the longitudinal axis is in line with a movable end portion of the actuator assembly and the motion transfer member.

Abstract: An apparatus for testing a semiconductor die and the method wherein there is provided a package having a cavity therein with a plurality of terminals in the package disposed at the periphery of the cavity. A semiconductor die to be tested and having a plurality of bond pads thereon is disposed in the cavity and an interconnecting layer having electrically conductive paths thereon is also disposed in the cavity, each of the paths having first and second spaced apart regions thereon, the first region of each path being aligned with and contacting a bond pad. An interconnection is provided between the second spaced apart region of each of the paths and one of the plurality of terminals. The second spaced apart region of each of the paths is preferably a bump aligned with and contacting one of the plurality of terminals. A compliant layer is preferably disposed over the interconnecting layer and provides a force causing engagement of at least the first spaced apart regions and the bond pads.

Abstract: An improved inkjet print head driver. The driver includes a source of predrive charge for a first, drive transistor coupled by its source and drain between an output node and a power supply, and having its gate coupled to the source of predrive charge. A second transistor is provided, adapted to receive an input signal at its gate. A third, control transistor is coupled by its source and drain between the gate of the first transistor and the second transistor, the second transistor being coupled by its source and drain between the third transistor and ground. Optionally, a resistor is coupled in parallel with the third transistor, i.e., across the source and drain of the third transistor.

Abstract: A method (100) of fabricating an electronic device (200) formed on a semiconductor wafer. The method forms a dielectric layer (226) in a fixed position relative to the wafer, where the dielectric layer comprises an atomic concentration of each of silicon, carbon, and oxygen. After the forming step, the method exposes (118) the electronic device to a plasma such that the atomic concentration of carbon in a portion of the dielectric layer is increased and the atomic concentration of oxygen in a portion of the dielectric layer is decreased. After the exposing step, the method forms a barrier layer (120) adjacent at least a portion of the dielectric layer.

Abstract: The present invention provides a system and method for high resolution current measurements of an integrated circuit (13). With the present invention, no DFT circuits are required. Leakage current characterizing an integrated circuit is determined for at least one logic state of the integrated circuit from a sum of a first and second current measurement. A voltage source (15) and a current source (17) are used at different settings for each measurement and the measurements are summed for evaluation with an expected value.

Abstract: A slot-aligned IQ data buffer scheme has a third buffer that allows a processing engine to slide the selection of a vector to be processed so that it aligns with the framing of the data. This is particularly advantageous for CDMA and WCDMA systems where there are overlaying coded data streams, each with its own frame timing, since data is processed cleanly at boundaries in the data such that the processing hardware can be minimized. A first level of muxing selects a pair of buffers having the data to be processed from among three buffers. A second level of muxing selects the sample number required. The third level of muxing selects the correct chips for the alignment of the slot. The third stage is implemented with a barrel shifter to minimize hardware generally associated with use of multiplexing.

Abstract: A method for generating digital filters for equalizing a loudspeaker. First digital data is provided, for a tolerance range for a target response curve of sound level versus frequency for the loudspeaker. Second digital data is generated, for an actual response curve of sound level versus frequency for the loudspeaker. The first digital data is compared with the second digital data and it is determined whether the actual response curve is within the tolerance range. If the actual response curve is not within the tolerance range, digital audio filters are iteratively generated, and the digital audio filters are applied to the second digital data to generate third digital data for a compensated response curve. The frequency, amplitude and bandwidth of the digital audio filters are automatically optimized until the compensated response curve is within the tolerance range or a predetermined limit on the number of digital audio filters has been reached, whichever occurs first.

Abstract: A filter circuit with two 2nd order stages cascaded in sequence. The first stage is implemented with high quality (Q) factor, and the second stage is implemented with a low Q factor and an imaginary zero. The first stage is designed to further eliminate the unwanted frequency components. The imaginary zero in the second stage eliminates the noise present in the output of the first stage due to the requirement of high Q in the first stage. Any additional noise introduced by the second stage is minimal due to the low Q of the second stage. Each stage may be implemented using only a single operational amplifier when the first stage generates a differential output signal.

Abstract: A Seebeck effect thermal sensor is formed in an integrated fashion with a power-dissipating device such as a power MOSFET. The integrated device generates a temperature difference between a relatively cold peripheral area and a relatively warm central area, the temperature difference having a known relationship to electrical operating conditions of the device. A structure for a power MOSFET includes two side-by-side arrays of source/drain diffusions. The Seebeck sensor has warm junctions at the central area and cold junctions at the peripheral area, and generates an electrical output signal having a known relationship to the temperature difference between the peripheral and central areas to provide an indication of the electrical operating conditions of the device. One Seebeck sensor includes alternating metal and polysilicon traces, wherein the polysilicon traces lie between source and drain diffusions of a power MOSFET just as do active polysilicon gates.

Abstract: The present invention provides an apparatus and method for reducing the voltage stress in a single-stage single-switch (SSSS) converter by modulating the predetermined operating frequency of the converter lower responsive to increasing voltage stress. A control circuit (116) and associated cooperable frequency setting capacitance (CT) and resistance (RT) are coupled to the primary circuit (112) and the secondary circuit (114) of the SSSS converter via a switch (120). A frequency foldback device (180) is coupled to CT or RT and cooperable therewith to lower bus voltage stress by modulating the switch frequency. The operating frequency is modulated (i.e. reduced) from the predetermined operating frequency upon detection of a voltage threshold transition.

Abstract: A temperature sensing system (30) that providing at least one detect signal related to temperature in an integrated circuit is presented. This system uses one thermal sensing circuit (40) to detect two or more temperature thresholds (t2, t3) and differentiates the temperature thresholds using time multiplexed logic control. The system (80) capable of detecting more than two temperatures includes the thermal sensing circuit (90) and a decode circuit (92) with at least one detect latch (100). Optionally, the system may include a hysteresis circuit (60). The thermal sensing circuit (40), connected to the integrated circuit, generates a detect signal (D4) in response to the a temperature selection signal (T1). This flexible on-board temperature monitoring solution reduces the cost of thermal feedback sensing by reducing die area and improves the correlation of detected temperatures. In addition, this solution reduces the possibility of mismatch and tracking errors between two or more sense elements.

Abstract: A semiconductor package production method containing a step in which a bond layer made of a single-layer film thermoset bond is provided on the back of a wafer on which many semiconductor devices are formed, a dicing tape is pasted onto its bond layer side, and the bond layer and the wafer are diced simultaneously in order to obtain semiconductor devices with the bond layer, and a step in which the semiconductor devices with the bond layer are detached from the dicing tape and die-attached to interposing substrates serving as bodies to which they are bonded; wherein, the aforementioned film thermoset bond contains an epoxy resin, an epoxy resin hardener, and a phenoxy resin as well as 50-80 wt % of spherical silica, and the bond layer is 100 &mgr;m or thicker. A semiconductor device made by this method and a wafer for use with this method.

Abstract: As IC circuit density increases, the testing of ICs becomes more complex and costly for the IC manufacturers. A test system and method achieves cost reduction in testing by permitting simultaneous testing of a plurality of semiconductor die. The testing can occur while the die are on a wafer or after the die have been packaged.

Abstract: A user interface that allows a user to visually understand, inspect, and manipulate a compiled application program as a function of compiler options, such as, code size and speed, is provided.

Abstract: A method of fabricating a transistor includes providing a semiconductor substrate having a surface and forming a nitride layer outwardly of the surface of the substrate. The nitride layer is oxidized to form a nitrided silicon oxide layer comprising an oxide layer beneath the nitride layer. A high-K layer is deposited outwardly of the nitride layer, and a conductive layer is formed outwardly of the high-K layer. The conductive layer, the high-K layer, and the nitrided silicon oxide layer are etched and patterned to form a gate stack. Sidewall spacers are formed outwardly of the semiconductor substrate adjacent to the gate stack, and source/drain regions are formed in the semiconductor substrate adjacent to the sidewall spacers.