Abstract: A pushbutton resettable circuit breaker is shown having features to prevent manual opening by simply pulling outwardly on the pushbutton. In one embodiment, the pushbutton (16) is formed with slots (16b) which are configured to provide a reaction surface essentially inaccessible without a special purpose contact opening tool (30). The tool is provided with portions that are insertable into the slots and into engagement with the reaction surfaces for pulling the pushbutton out and manually opening the contacts. In a second embodiment, a small aperture 16k is formed through the rating tab and top and wall of the button and in alignment with a movable plunger (28). A special purpose contact opening tool (32, 34) can be inserted through the aperture to apply a force to the plunger and mechanically trip the circuit breaker.

Abstract: A process for manufacturing a wafer from a layer of material such as silicon and having a multiplicity of MEMS devices such as mirrors with gimbals formed thereon is disclosed. The features of the devices on the wafer as well as the boundaries which separate individual devices are defined by lines having a constant width so as to avoid microloading effects. Waste areas of the layer of material which are greater than the constant line width are removed as breakout pieces during the release process.

Abstract: A drive circuit including circuitry that can be easily adjusted, the output drive current can be kept balanced, and high-precision drive current can be supplied to the load circuit. Clamp circuit 10 is furnished to hold the drain voltage of current output transistor QN12, which supplies drive current to a load resistor. When transistor QN12 is in a conducting state, drain voltage VA of transistor QN12 is held at approximately the same level as source voltage VD of transistor QN14 by clamp circuit 10. So rise and fall in the drain output current of transistor QN12 can be kept balanced, and rise and fall delay time can be made approximately equal for input signal Sin.

Abstract: An emitter coupled pair transconductor circuit includes: an emitter couple pair 20 and 21; and a tail current source coupled to the emitter couple pair wherein the tail current source provides a tail current that is a hyperbolic cosine function relative to a differential input signal. This solution transforms the output current of an emitter couple pair transconductor from a hyperbolic tangent to a hyperbolic sine by using a hyperbolic cosine comparator for the biasing. By doing this, the transconductor has a similar speed behavior to a second-generation current conveyor and is more precise. This transformation makes a regular transconductor very fast without changing its parameters.

Abstract: A power integrated circuit architecture (10) having a high side transistor (100) interposed between a control circuit (152) and a low side transistor (100) to reduce the effects of the low side transistor on the operation of the control circuit. The low side transistor has a heavily p-doped region (56) designed to reduce minority carrier lifetime and improve minority carrier collection to reduce the minority carriers from disturbing the control circuit. The low side transistor has a guardring (16) tied to an analog ground, whereby the control circuit is tied to a digital ground, such that the collection of the minority carriers into the analog ground does not disturb the operation of the control circuit. The low side transistor is comprised of multiple transistor arrays (90) partitioned by at least one deep n-type region (16), which deep n-type region forms a guardring about the respective transistor array.

Abstract: A method of preventing seam defects on narrow, isolated lines of 0.3 micron or less during CMP process is provided. The solution is to change the size of features of dummy metal structures on the same layer as the metal layer to have a width that is about 0.6 micron or less so that during the electroplating the deposition rate in the features is similar to the narrow, isolated lines. The density, shape, and proximity of the dummy metal structures further prevents the seam defects during CMP processing by preventing Galvanic corrosion.

Abstract: A secure computing system prevents unauthorized use of compressed video data stored in a first-in-first-out memory buffer in a set top box. A single integrated circuit includes a data processor and a chip identity read only register storing a unique chip identity number fixed during manufacture. The data processor encrypts the compressed video data stream using the chip identity number as an encryption key. This encrypted data is stored in and recalled from a FIFO buffer. The data processor then decrypts the recalled data employing at least a part of the chip identity number as the decryption key. Using technique the compressed video data stream temporarily stored in compressed form in the FIFO buffer can only be employed by the particular data processor having the unique chip identity number.

Abstract: An adjustable impedance boosting circuit for a magneto-resistive head in a gain stage beyond the input gain stage. The boosting circuit compensates for a frequency pole of the head leads by introducing a zero in proportion to the resistance of the magneto-resistive element and with selectable circuit parameters to further adjust the pole compensation. The invention includes selectively adjusting the sensitivity of the pole compensation to changes in the resistance of the head, selectively adjusting the peak compensation, and adjusting the frequency of the compensating zero.

Abstract: A ferroelectric device fabrication process is described in which ferroelectric device contaminant substances (e.g., Pb, Zr, Ti, and Ir) that are incompatible with standard CMOS fabrication processes are tightly controlled. In particular, specific etch chemistries have been developed to remove incompatible substances from the backside and edge surfaces of the substrate after a ferroelectric device has been formed. In addition, a sacrificial layer may be disposed over the bottom and edge surfaces (and, in some embodiments, the frontside edge exclusion zone surface) of the substrate to assist in the removal of difficult-to-etch contaminants (e.g., Ir). In this way, the ferroelectric device fabrication process may be integrated with a standard semiconductor fabrication process, whereby ferroelectric devices may be formed together with semiconductor integrated circuits without substantial risk of cross-contamination through shared equipment (e.g., steppers, metrology tools, and the like).

Abstract: In one embodiment, an integrated circuit includes a heat generating structure within a dielectric region and one or more substantially horizontally arranged heat dissipation layers within the dielectric region. Each heat dissipation layer includes electrically inactive thermally conductive structures, at least two such structures in at least one such layer being substantially horizontally connected and thermally coupled to one another within the layer. The electrically inactive thermally conductive structures cooperate to facilitate dissipation of heat from the heat generating structure. In another embodiment, an integrated circuit includes one or more heat generating structures within a dielectric region and electrically inactive thermal posts formed at least partially within the dielectric region. At least one such post is substantially horizontally connected and thermally coupled to another such post.

Abstract: The marking of identification and orientation information along the edge (E) of a semiconductor wafer (20, 20′) is disclosed. The information may be marked by way of laser marking at one or more locations (10) along a flat portion (14) or bevel (12t, 12b) of the edge (E) of the wafer (20, 20′). The wafer marking (10) may be encoded, for example by way of a 2-D bar code. A system (30) for reading the identification information from wafers (20, 20′) in a carrier (32) is also disclosed. The system (30) includes a sensor (36) for sensing reflected light from the wafer markings (10) along the wafer edge (E), and for decoding identification and orientation therefrom. A motor (38), under the control of feedback (RFB) from the sensor (36), rotates the wafers (20, 20′) by way of a roller (39) until the wafer marking (10) is in view by the sensor (36). A processing system (40), which includes a rotatable chuck (41) upon which the wafer (20, 20′) is placed, is also disclosed.

Abstract: A graphical user interface uses a representation of a polyhedron, such as a cube (44), having images on each face (46) for representing multiple desktops used in conjunction with an operating system. By pressing on faces of the cube (44), the computer switches to the selected desktop (42). The cube (44) may be rotated to allow the user to select from an unlimited number of desktops (42).

Abstract: An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test pins on the integrated circuit and 1149.1 Test Access Ports (TAP) of the plurality of circuits to be tested. The TAP Linking Module operates in response to 1149.1 scan operations from a tester connected to the test pins to selectively switch between 1149.1 TAPs to enable test access between the tester and plurality of circuits. The TAP Linking Module's 1149.1 TAP switching operation is based upon augmenting 1149.1 instruction patterns to affix an additional bit or bits of information which is used by the TAP Linking Module for performing the TAP switching operation.

Abstract: A distributed power device (100) including a plurality of tank regions (90) separated from one another by a deep n-type region (16), and having formed in each tank region a plurality of transistors (50). The plurality of transistors (50) in each tank region are interconnected to transistors in other tank regions to form a large power FET, whereby the deep n-type regions isolate the tank regions from one another. A first parasitic diode (D5) is defined from each tank region to a buried layer, and a second parasitic diode (D4) is defined between the buried layer and a substrate. The deep n-type regions distribute the first and second parasitic diodes with respect to the plurality of tank regions, preferably comprised of a P-epi tank. The deep n-type regions also distribute the resistance of an NBL layer (14) formed under the tank regions.

Abstract: A capacitor under bitline DRAM memory cell and method for its fabrication provides a high density memory cell with the capacitor formed in the PMD layer. The memory cell utilizes several variations of storage contact pillar structures as, for example, a storage plate of the memory cell capacitor formed within a trench in the PMD layer. This capacitor plate structure is overlaid with a capacitor dielectric layer which is overlaid with another conductive layer, for example, the M1 layer to form the other capacitor plate. An access transistor formed between substrate active regions and a word line, is in electrical communication with a bit line contact, the storage contact capacitor plate, and the word line respectively. The high density memory cell benefits from the simple standard processes common to logic processes, and in one embodiment requiring only one additional masking step.

Abstract: A method for manufacturing a semiconductor device that comprises forming an oxide layer over a substrate. A polysilicon layer is disposed outwardly from the oxide layer, wherein the polysilicon layer forms a floating gate. A PSG layer is disposed outwardly from the polysilicon layer and planarized. The device is pattern etched to form a capacitor channel, wherein the capacitor channel is disposed substantially above the floating gate formed from the polysilicon layer. A dielectric layer is formed in the capacitor channel disposed outwardly from the polysilicon layer. A tungsten plug operable to substantially fill the capacitor channel is formed.

Abstract: An audio player permits compressed or uncompressed audio CDs to be played. The preferred player includes a spindle motor control that causes the CD to be spun at a constant linear velocity that is commensurate with the encoding rate of the file being played. In this manner, the data can be continuously pulled of the CD at just the right rate so that, after being decoded and decompressed, the data can be played. The player also dynamically adjusts its constant linear velocity to the encoding rate of the file being played to permit files on the same disc having different encoding rates to be played.

Abstract: A wireless base station (15) for transmitting spread spectrum signals is disclosed. The base station (15) includes a peak compression unit (16), which is comprised of a sequence of peak detection and cancellation circuits (32). Each peak detection and cancellation circuit (32) detects and compresses identified peaks. The further stages of peak detection and cancellation circuits (32) serve to reduce peaks that, as a result of “peak regrowth”, are caused at sample points near to a reduced peak point. According to one disclosed embodiment, a peak sample point is not qualified for compression unless a number of sample points subsequent to the peak all have lower magnitude than that of the peak. The cancellation pulses applied by the peak detection and cancellation circuits (32) may be generated by a finite impulse response (FIR) filter pulse, or alternatively by a minimum phase infinite impulse response (IIR) pulse.

Abstract: A conventional volatile SRAM cell is modified into a non-volatile, read only memory cell. This permits a device whose design currently includes on-chip SRAM, but no ROM, to have nonvolatile, read only memory with minimal redesign and development effort. The modifications made to the already present SRAM are fairly minimal resulting in much of the modified SRAM being largely unchanged. Because existing on chip, volatile memory is used largely as is with fairly minimal modifications to make the memory non-volatile, the time-to-market for such a device is much shorter than it would have been had the device been redesigned to include conventional ROM.

Abstract: A method for fabricating a leadframe structure comprising a chip mount pad and a plurality of lead segments, each having a first end near the mount pad and a second end remote from said mount pad. The structure is formed from a sheet-like starting material. In a first plating system, the leadframe is plated with a layer of nickel. Next, the second segment ends are selectively masked and a layer of palladium is selectively plated on the nickel layer on the exposed chip pad and first segments ends in a thickness suitable for wire bonding attachment. In a second plating system, the chip pad and first segment ends are selectively masked and a pure tin layer is selectively plated on the nickel layer on the exposed second segment ends in a thickness suitable for parts attachment.